Setting Up The Quad Spi Flash Controller - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Setting Up the Quad SPI Flash Controller

The following steps describe how to set up the quad SPI controller:
1. Wait until any pending operation has completed.
2. Disable the quad SPI controller with the quad SPI enable field (
3. Update the
and direct writes and reads.
4. If mode bit enable bit (
(
modebit
5. Update the
Parts or all of this register might have been updated after initialization. The number of address bytes is
a key configuration setting required for performing reads and writes. The number of bytes per page is
required for performing any write. The number of bytes per device block is only required if the write
protect feature is used.
6. Update the device delay register (
This register allows the user to adjust how the chip select is driven after each flash access. Each device
may have different timing requirements. If the serial clock frequency is increased, these timing require‐
ments become more critical. The numbers specified in this register are based on the period of the
qspi_ref_clk
be reasserted after it has been deasserted. When the device is operating at 100 MHz, the clock period is
10 ns, so 40 ns extra is required. If the
specify a value of at least 16 to the clock delay for chip select deassert field (
7. Update the
This register only affects direct access mode.
8. Set up and enable the write protection registers (
protection is required.
9. Enable required interrupts through the
10.Set up the
11.Update the read data capture register (
The Cyclone V pre-loader fills in this register with a value when the calibration routine is run at boot-
up. To modify this value, you may refer to the "QSPI Timing" section in the Cyclone V Data Sheet. This
register delays when the read data is captured and can help when the read data path from the device to
the quad SPI controller is long (which is relative to the hardware layout and design) and the device
clock frequency is high.
12.Enable the quad SPI controller with the
Related Information
Cyclone V Device Datasheet
Indirect Read Operation with DMA Disabled
The following steps describe the general software flow to set up the quad SPI controller for indirect read
operation with the DMA disabled:
1. Perform the steps described in the
2. Set the flash memory start address in the
3. Set the number of bytes to be transferred in the
4. Set the indirect transfer trigger address in the
Quad SPI Flash Controller
Send Feedback
field of the
instwidth
enmodebits
).
register as needed.
devsz
delay
clock. For example, some devices need 50 ns minimum time before the slave select can
register as needed.
remapaddr
field of the
bauddiv cfg
Setting Up the Quad SPI Flash Controller
register with the instruction type you wish to use for indirect
devrd
) of the register is enabled, update the mode bit register
devrd
).
clock is running at 400 MHz (2.5 ns period),
qspi_ref_clk
,
wrprot lowwrprot
register.
irqmask
register to define the required clock frequency of the target device.
) if you need to change the auto-filled value.
rddatacap
field of the register.
en cfg
Setting Up the Quad SPI Flash Controller
register.
indrdstaddr
register.
indrdcnt
indaddrtrig
) of the register.
en cfg
) of the
nss
, and ) when write
uppwrprot
on page 15-15 section.
register.
15-15
register.
delay
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