Altera cyclone V Technical Reference page 376

5-182
GPLMUX9
GPLMUX9
Selection between GPIO and LoanIO output and output enable for GPIO9 and LoanIO9. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5F8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GPLMUX9 Fields
Bit
0
sel
GPLMUX10
Selection between GPIO and LoanIO output and output enable for GPIO10 and LoanIO10. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5FC
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 9. 0 : LoanIO 9
controls GPIO/LOANIO[9] output and output enable
signals. 1 : GPIO 9 controls GPIO/LOANI[9] output
and output enable signals.
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Register Address
0xFFD085F8
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD085FC
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
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