Altera cyclone V Technical Reference page 514

Hard processor system

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comp_id_2 Fields

Component ID3

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

comp_id_3 Fields

Master Register Group Register Descriptions

Registers associated with master interfaces in the L3 Interconnect. Note that a master in the L3

Interconnect connects to a slave in a module.

L4 MAIN Register Descriptions

Registers associated with the L4 MAIN master. This master is used to access the APB slaves on the L4

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software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Base Address

System Interconnect

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