Altera cyclone V Technical Reference page 292

5-98
Pin Mux Control Group Register Descriptions
GPLINMUX64
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 64. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX65
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 65. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX66
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 66. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX67
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 67. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX68
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 68. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX69
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 69. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLINMUX70
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 70. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX0
Selection between GPIO and LoanIO output and output enable for GPIO0 and LoanIO0. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX1
Selection between GPIO and LoanIO output and output enable for GPIO1 and LoanIO1. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX2
Selection between GPIO and LoanIO output and output enable for GPIO2 and LoanIO2. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Altera Corporation
on page 5-169
on page 5-170
on page 5-171
on page 5-171
on page 5-172
on page 5-173
on page 5-174
on page 5-174
on page 5-175
on page 5-176
cv_5v4
2016.10.28
System Manager
Send Feedback