Altera cyclone V Technical Reference page 557

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
write_qos Fields
Bit
3:0
pri
fn_mod
Sets the block issuing capability to multiple or single outstanding transactions.
Module Instance
l3regs
Offset:
0x44108
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
System Interconnect
Send Feedback
29
28
27
26
13
12
11
10
Reserved
Name
QoS (Quality of Service) value for the write channel.
A higher value has a higher priority.
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
fn_mod
21
20
19
18
5
4
3
2
RW 0x0
Access
Register Address
0xFF844108
21
20
19
18
5
4
3
2
7-109
17
16
1
0
pri
Reset
RW
0x0
17
16
1
0
wr
rd
RW
RW 0x0
0x0
Altera Corporation

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