Altera cyclone V Technical Reference page 791

cv_5v4
2016.10.28
dramodt Fields
Bit
7:4
cfg_read_odt_chip
3:0
cfg_write_odt_chip
dramaddrw
This register configures the width of the various address fields of the DRAM. The values specified in this
register must match the memory devices being used.
Module Instance
sdr
Offset:
0x502C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30 29
15 14 13
csbits
RW 0x0
SDRAM Controller Subsystem
Send Feedback
Name
This register controls which
reads. Bits[5:4] select the
and bits[7:6] select the
For example, a value of 0x9 asserts
accesses
field can be set to 0x1 is there is only one chip select
available.
This register controls which
writes. Bits[1:0] select the
and bits[3:2] select the
CS0
. For example, a value of 0x9 asserts
CS1
accesses
field can be set to 0x1 is there is only one chip select
available.
Base Address
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
28 27 26 25
12 11 10 9
bankbits
RW 0x0
Description
pin is asserted during
ODT
pin that asserts with
ODT
pin that asserts with
ODT
and for accesses with
CS0 ODT[1]
pin is asserted during
ODT
pin that asserts with
ODT
pin that asserts with
ODT
and for accesses with
CS0 ODT[1]
0xFFC2502C
Bit Fields
24 23 22 21
Reserved
8 7 6
rowbits
RW 0x0
dramaddrw
Access
CS0
.
CS1
for
ODT[0]
. This
CS1
for
ODT[0]
. This
CS1
Register Address
20 19 18
5 4 3 2
colbits
RW 0x0
11-53
Reset
RW 0x0
RW 0x0
17 16
1 0
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