Altera cyclone V Technical Reference page 6

TOC-6
CoreSight Debug and Trace Programming Model..............................................................................10-16
CoreSight Debug and Trace Address Map and Register Definitions................................................ 10-22
Document Revision History...................................................................................................................10-27
SDRAM Controller Subsystem..........................................................................11-1
Features of the SDRAM Controller Subsystem......................................................................................11-1
SDRAM Controller Subsystem Block Diagram..................................................................................... 11-2
SDRAM Controller Memory Options.....................................................................................................11-3
SDRAM Controller Subsystem Interfaces.............................................................................................. 11-4
Memory Controller Architecture.............................................................................................................11-6
Functional Description of the SDRAM Controller Subsystem..........................................................11-10
SDRAM Power Management................................................................................................................. 11-24
DDR PHY................................................................................................................................................. 11-25
Clocks........................................................................................................................................................ 11-25
Resets......................................................................................................................................................... 11-26
Port Mappings.......................................................................................................................................... 11-26
Initialization..............................................................................................................................................11-27
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Trace Funnel................................................................................................................................... 10-5
CoreSight Trace Memory Controller...........................................................................................10-5
AMBA Trace Bus Replicator.........................................................................................................10-6
Trace Port Interface Unit...............................................................................................................10-6
Embedded Cross Trigger System................................................................................................. 10-6
Program Trace Macrocell............................................................................................................10-11
HPS Debug APB Interface.......................................................................................................... 10-11
FPGA Interface.............................................................................................................................10-11
Debug Clocks................................................................................................................................10-14
Debug Resets................................................................................................................................ 10-15
Coresight Component Address..................................................................................................10-16
STM Channels.............................................................................................................................. 10-17
CTI Trigger Connections to Outside the Debug System........................................................10-19
Configuring Embedded Cross-Trigger Connections.............................................................. 10-20
System Trace Macrocell (STM) Module Address Map........................................................... 10-23
Debug Access Port (DAP) Module Address Map....................................................................10-23
MPU Address Map...................................................................................................................... 10-25
MPU L2 Cache Controller (L2C-310) Module Address Map................................................10-26
MPU Subsystem Interface.............................................................................................................11-4
L3 Interconnect Interface..............................................................................................................11-4
CSR Interface.................................................................................................................................. 11-5
FPGA-to-HPS SDRAM Interface.................................................................................................11-5
Multi-Port Front End.....................................................................................................................11-7
Single-Port Controller................................................................................................................... 11-8
MPFE Operation Ordering.........................................................................................................11-10
MPFE Multi-Port Arbitration.................................................................................................... 11-10
MPFE SDRAM Burst Scheduling.............................................................................................. 11-13
Single-Port Controller Operation.............................................................................................. 11-14
DDR Calibration.......................................................................................................................... 11-25
Taking the SDRAM Controller Subsystem Out of Reset ....................................................... 11-26
FPGA-to-SDRAM Protocol Details...........................................................................................11-28