Altera cyclone V Technical Reference page 43

2-6
Dividers
Variable
FIN = Input frequency
FREF = Reference frequency
= Post-scale counter
C
i
K = Internal post-scale counter in main PLL
M = numer + 1
N = denom + 1
Note: The reset values of numer and denom are 1 so that at reset, the M value is 2 and the N value is 2.
The register is used to program the M and N values. In the table below you can see which sections of
vco
the bit field are used to set the values of M and N.
vco
Table 2-3: VCO Register
Name
numer
denom
Unused clock outputs should be set to a safe frequency such as 50 MHz to reduce power consumption and
improve system stability.
Related Information
Clock Manager Address Map and Register Definitions
For the full bit field of the vco register, refer to the Address Map and Register Definitions section.
Dividers
Dividers subdivide the C0-C15 clocks produced by the PLL to lower frequencies. The main PLL C0-C2
clocks have an additional internal post-scale counter.
Altera Corporation
Value
Bit
3:15 0x1
16:21 0x1
-
-
i is 0-5 for each of the six counters
reset values are K = 2 for C0 K=4 for C1
and C2
Part of clock feedback path. VCO register is
used to program M value.
(Range 1 to 4096)
Part of input clock path. VCO register is
used to program N value.
(Range 0 to 64)
Reset Range
0 to 4095
0 to 63
on page 2-23
2016.10.28
Description
Description
Numerator in VCO
output frequency
equation.
Note: Bit 15 reserved.
Denominator in VCO
output frequency
equation.
Clock Manager
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