Altera cyclone V Technical Reference page 172

cv_5v4
2016.10.28
Bit
7
prd
6
pre
5
prr
4
ccd
FPGA Manager
Send Feedback
Name
Controls whether an interrupt for PR_DONE can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for PR_ERROR can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for PR_READY can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for CVP_CONF_
DONE can generate an interrupt to the interrupt
controller by not masking it. The unmasked status can
be read as well as the resultant status after masking.
Value
0x0
0x1
Description
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
4-29
gpio_intmask
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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