Altera cyclone V Technical Reference page 926

cv_5v4
2016.10.28
Bit
12
INT_act
11
unsup_cmd
10
locked_blk
9
pipe_cpybck_cmd_comp
8
erase_comp
7
program_comp
6
load_comp
5
erase_fail
4
program_fail
3
time_out
2
dma_cmd_comp
1
RSVD
0
ecc_uncor_err
intr_en2
Enables corresponding interrupt bit in interrupt register for bank 2
Module Instance
nandregs
Offset:
0x4C0
NAND Flash Controller
Send Feedback
Name
R/B pin of device transitioned from low to high
An unsupported command was received. This
interrupt is set when an invalid command is received,
or when a command sequence is broken.
The address to program or erase operation is to a
locked block and the operation failed due to this
reason
A pipeline command or a copyback bank command
has completed on this particular bank
Device erase operation complete
Device finished the last issued program command.
Device finished the last issued load command.
Erase failure occurred in the device on issuance of a
erase command. err_block_addr and err_page_addr
contain the block address and page address that failed
erase operation.
Program failure occurred in the device on issuance of
a program command. err_block_addr and err_page_
addr contain the block address and page address that
failed program operation.
Watchdog timer has triggered in the controller due to
one of the reasons like device not responding or
controller state machine did not get back to idle
A data DMA command has completed on this bank.
RSVD
Ecc logic detected uncorrectable error while reading
data from flash device.
0xFFB80000
Description
Base Address
13-105
intr_en2
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
R 0x0
RW 0x0
Register Address
0xFFB804C0
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