Altera cyclone V Technical Reference page 784

11-46
ctrlcfg
31 30
Reserved
15 14
reordere gendb gensb
n e
RW 0x0 RW
0x0
ctrlcfg Fields
Bit
25
bursttermen
24
burstintren
23
nodmpins
22
dqstrken
21:16
starvelimit
15
reorderen
14
gendbe
13
gensbe
Altera Corporation
29 28 27 26
13 12 11 10
cfg_ eccco eccen
e enabl rren
RW
e_
RW RW 0x0
ecc_
0x0 0x0
code_
overw
rites
RW
0x0
Name
Set to a one to enable the controller to issue burst
terminate commands. This must only be set when the
DRAM memory type is LPDDR2.
Set to a one to enable the controller to issue burst
interrupt commands. This must only be set when the
DRAM memory type is LPDDR2.
Set to a one to enable DRAM operation if no DM pins
are connected.
Enables DQS tracking in the PHY.
Specifies the number of DRAM burst transactions an
individual transaction will allow to reorder ahead of it
before its priority is raised in the memory controller.
This bit controls whether the controller can re-order
operations to optimize SDRAM bandwidth. It should
generally be set to a one.
Enable the deliberate insertion of double bit errors in
data written to memory. This should only be used for
testing purposes.
Enable the deliberate insertion of single bit errors in
data written to memory. This should only be used for
testing purposes.
Bit Fields
25 24 23 22
burst burst nodmp dqstr
terme intre ins ken
n n
RW RW
RW RW 0x0 0x0
0x0 0x0
9 8 7 6
addrorder
RW 0x0
Description
21 20 19 18
starvelimit
RW 0x0
5 4 3 2
membl
RW 0x0
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
1 0
memtype
RW 0x0
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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