Altera cyclone V Technical Reference page 70

cv_5v4
2016.10.28
31 30
15 14
stat Fields
Bit
0
busy
Main PLL Group Register Descriptions
Contains registers with settings for the Main PLL.
Offset:
0x40
vco on page 2-34
Contains settings that control the Main PLL VCO. The VCO output frequency is the input frequency
multiplied by the numerator (M+1) and divided by the denominator (N+1). The VCO input clock source
is always eosc1_clk. Fields are only reset by a cold reset.
misc on page 2-36
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
mpuclk
on page 2-37
Contains settings that control clock mpu_clk generated from the C0 output of the Main PLL. Only reset by
a cold reset.
mainclk
on page 2-38
Contains settings that control clock main_clk generated from the C1 output of the Main PLL. Only reset
by a cold reset.
Clock Manager
Send Feedback
29 28 27 26
13 12 11 10
Name
This read only bit indicates that the Hardware
Managed clock's state machine is active. If the state
machine is active, then the clocks are in transition.
Software should poll this bit after changing the source
of internal clocks when writing to the BYPASS, CTRL
or DBCTRL registers. Immediately following writes to
any of these registers, SW should wait until this bit is
IDLE before proceeding with any other register writes
in the Clock Manager. The reset value of this bit is
applied on a cold reset; warm reset has no effect on
this bit.
Value
0x0
0x1
Main PLL Group Register Descriptions
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Clocks stable
Clocks in transition
21 20 19 18
5 4 3 2
Access
RO
2-33
17 16
1 0
busy
RO 0x0
Reset
0x0
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