Altera cyclone V Technical Reference page 155

Hard processor system

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gpio_config_reg1

Provides status fields for software for the FPGA Manager. The Mode field tells software what configuration

phase the FPGA currently is in. For regular configuration through the PINs or through the HPS, these

states map directly to customer configuration documentation. For Configuration Via PCI Express (CVP),

the IOCSR configuration is done through the PINS or through HPS. Then the complete configuration is

done through the PCI Express Bus. When CVP is being done, InitPhase indicates only IOCSR

configuration has completed. CVP_CONF_DONE is available in the CB Monitor for observation by

software. The MSEL field provides a read only register for software to read the MSEL value driven from the

external pins.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Altera Corporation

Base Address

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

This read-only field allows software to observe the

MSEL inputs from the device pins. The MSEL pins

define the FPGA configuration mode.

16-bit Passive Parallel with Fast Power on Reset

Delay; No AES Encryption; No Data Compres‐

sion. CDRATIO must be programmed to x1

Configuration Register 1

FPGA Manager

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