Altera cyclone V Technical Reference page 549

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
fn_mod_ahb Fields
Bit
1
wr_incr_override
0
rd_incr_override
read_qos
QoS (Quality of Service) value for the read channel.
Module Instance
l3regs
Offset:
0x42100
System Interconnect
Send Feedback
29
28
27
26
13
12
11
10
Name
Controls how AHB-lite write burst transactions are
converted to AXI tranactions.
Value
0x0
0x1
Controls how AHB-lite read burst transactions are
converted to AXI tranactions.
Value
0x0
0x1
0xFF800000
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Description
The L3 Interconnect converts AHB-lite write
bursts to AXI transactions in accordance with
the default behavior as specified in the ARM
NIC-301 documentation.
The L3 Interconnect converts AHB-lite write
bursts to AXI single transactions.
Description
The L3 Interconnect converts AHB-lite read
bursts to AXI transactions in accordance with
the default behavior as specified in the ARM
NIC-301 documentation.
The L3 Interconnect converts AHB-lite read
bursts to AXI single transactions.
Base Address
read_qos
21
20
19
18
5
4
3
2
Access
Register Address
0xFF842100
7-101
17
16
1
0
wr_
rd_incr_
incr_
override
overr
RW 0x0
ide
RW
0x0
Reset
RW
0x0
RW
0x0
Altera Corporation

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