Altera cyclone V Technical Reference page 485

cv_5v4
2016.10.28
Bit
0
spis0
l4sp
Controls security settings for L4 SP peripherals.
Module Instance
l3regs
Offset:
0xC
Access:
WO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
System Interconnect
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Name
Controls whether secure or non-secure masters can
access the SPI Slave 0 slave.
Value
0x0
0x1
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
sptim
er1
WO
0x0
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
can1 can0 uart1 uart0
WO WO WO WO
0x0 0x0 0x0 0x0
Access
Register Address
0xFF80000C
21 20 19 18
5 4 3 2
i2c3 i2c2 i2c1 i2c0
WO WO WO WO
0x0 0x0 0x0 0x0
7-37
l4sp
Reset
WO 0x0
17 16
1 0
sptim sdrregs
er0
WO 0x0
WO
0x0
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