Altera cyclone V Technical Reference page 687

cv_5v4
2016.10.28
Bit
8:4
user
vid2wr_s
The Write AXI Master Mapping Status Register contains the configured USER, ADDR page, and ID
signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID.
Module Instance
acpidmap
Offset:
0x34
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
force Reserved
RO 0x1
15 14
Reserved
vid2wr_s Fields
Bit
31
force
27:16
mid
13:12
page
8:4
user
Cortex-A9 Microprocessor Unit Subsystem
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Name
This value is propagated to SCU as ARUSERS.
0xFF707000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
page Reserved
RO 0x0
Name
Set to 1 to force the mapping between the 12-bit ID
and 3-bit virtual ID N. Set to 0 to allow the 3-bit ID N
to be dynamically allocated.
The 12-bit ID of the master to remap to 3-bit virtual
ID N, where N is the 3-bit ID to use.
AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB
memory region.
This value is propagated to SCU as AWUSERS.
Description
Base Address
Bit Fields
25 24 23 22
RO 0x4
9 8 7 6
user
RO 0x1
Description
vid2wr_s
Access
Register Address
0xFF707034
21 20 19 18
mid
5 4 3 2
Reserved
Access
9-51
Reset
RO 0x1
17 16
1 0
Reset
RO 0x1
RO 0x4
RO 0x0
RO 0x1
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