Booting Operation For Emmc And Mmc - Altera cyclone V Technical Reference

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Booting Operation for eMMC and MMC

• CRC error on command—If a CRC error is detected for a command, the CE-ATA card device does not
send a response, and a response timeout is expected from the controller. The ATA layer is notified that
an MMC transport layer error occurred.
• Write operation—Any MMC transport layer error known to the card device causes an outstanding
ATA command to be terminated. The ERR bits are set in the ATA status registers and the appropriate
error code is sent to the Error Register (Error) on the ATA card device.
If the device interrupt bit of the CE-ATA card (the nIEN bit in the ATA control register) is set to 0, the
CCS is sent to the host.
If the device interrupt bit is set to 1, the card device completes the entire data unit count if the host
controller does not abort the ongoing transfer.
Note: During a multiple-block data transfer, if a negative CRC status is received from the card device,
the data path signals a data CRC error to the BIU by setting the
to 1. It then continues further data transmission until all the bytes are transmitted.
• Read operation—If MMC transport layer errors are detected by the host controller, the host completes
the ATA command with an error status. The host controller can issue a CCSD command followed by a
STOP_TRANSMISSION (CMD12) command to abort the read transfer. The host can also transfer the
entire data unit count bytes without aborting the data transfer.
Booting Operation for eMMC and MMC
This section describes how to set up the controller for eMMC and MMC boot operation.
Note: The BootROM and initial software do not use the boot partitions that are in the MMC card. This
means that there is no boot partition support of the SD/MMC controller.
Boot Operation by Holding Down the CMD Line
The controller can boot from MMC4.3, MMC4.4, and MMC4.41 cards by holding down the CMD line.
For information about this boot method, refer to the following specifications, available on the JEDEC
website:
• JEDEC Standard No. 84-A441
• JEDEC Standard No. 84-A44
• JEDEC Standard No. JESD84-A43
Related Information
www.jedec.org
For more information about this boot method, refer to the following JEDEC Standards available on the
JEDEC website: No. 84-A441, No. 84-A44, and No. JESD84-A43.
Boot Operation for eMMC Card Device
The following figure illustrates the steps to perform the boot process for eMMC card devices. The detailed
steps are described following the flow chart.
Altera Corporation
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bit in the
dcrc rintsts
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SD/MMC Controller
cv_5v4
2016.10.28
register
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