Altera cyclone V Technical Reference page 154

cv_5v4
2016.10.28
FPGA Manager Module
Register
stat on page 4-12
ctrl on page 4-15
dclkcnt on page 4-18
dclkstat on page 4-
19
gpo on page 4-20
gpi on page 4-21
misci on page 4-21
Configuration Monitor (MON) Registers
Register
gpio_inten on page 4-
24
gpio_intmask
4-27
gpio_inttype_level
page 4-30
gpio_int_polarity
page 4-33
gpio_intstatus
page 4-36
gpio_raw_intstatus
page 4-39
gpio_porta_eoi
page 4-41
gpio_ext_porta
page 4-44
gpio_ls_sync
4-45
gpio_ver_id_code
page 4-46
gpio_config_reg2
page 4-47
FPGA Manager
Send Feedback
Offset Width Acces
0x0
0x4
0x8
0xC
0x10
0x14
0x18
Offset Width Acces
0x830
on page 0x834
on 0x838
on 0x83C
on 0x840
on 0x844
on 0x84C
on 0x850
on page 0x860
on 0x86C
on 0x870
FPGA Manager Module Address Map
Reset Value
s
32 RW 0x45
32 RW 0x200
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x0
32 RO 0x0
Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x0
32 RO 0x0
32 WO 0x0
32 RO 0x0
32 RW 0x0
32 RO 0x3230382A
32 RO 0x39CEB
Description
Status Register
Control Register
DCLK Count Register
DCLK Status Register
General-Purpose Output Register
General-Purpose Input Register
Miscellaneous Input Register
Description
Interrupt Enable Register
Interrupt Mask Register
Interrupt Level Register
Interrupt Polarity Register
Interrupt Status Register
Raw Interrupt Status Register
Clear Interrupt Register
External Port A Register
Synchronization Level Register
GPIO Version Register
Configuration Register 2
Altera Corporation
4-11