Altera cyclone V Technical Reference page 118

cv_5v4
2016.10.28
Module Reset Signal
i2c_rst_n[3:0]
uart_rst_n[1:0]
spim_rst_n[1:0]
spis_rst_n[1:0]
sdmmc_rst_n
can_rst_n[1:0]
gpio_rst_n[2:0]
dma_rst_n
sdram_rst_n
Table 3-5: PER2 Group, Generated Module Resets
Module Reset Signal
dma_periph_if_rst_n[7:0]
Table 3-6: Bridge Group, Generated Module Resets
Module Reset Signal
hps2fpga_bridge_rst_n
fpga2hps_bridge_rst_n
lwhps2fpga_bridge_rst_n
Reset Manager
Send Feedback
Description
2
Resets each I C controller
Resets each UART
Resets SPI master controller
Resets SPI slave controller
Resets SD/MMC controller
Resets each CAN controller
Resets each GPIO interface
Resets DMA controller
Resets SDRAM subsystem
(resets logic associated with
cold or warm reset)
Description
DMA controller request
interface from FPGA
fabric to DMA controller
Description
Resets HPS-to-FPGA
AMBA Advanced
®
eXtensible Interface
(AXI ) bridge
™
Resets FPGA-to-HPS AXI
bridge
Resets lightweight HPS-to-
FPGA AXI bridge
Module Reset Signals
Reset Cold Warm
Domai Reset Reset
n
System X X
System X X
System X X
System X X
System X X
System X X
System X X
System X X
System X X
Reset Cold Warm
Domai Reset Reset
n
Syste X X
m
Reset Cold Warm
Domai Reset Reset
n
Syste X X
m
Syste X X
m
Syste X X
m
3-7
Software
Debug
Deassert
Reset
X
X
X
X
X
X
X
X
X
Debu Software
g Deassert
Reset
X
Debu Software
g Deassert
Reset
X
X
X
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