System Interconnect Master Properties - Altera cyclone V Technical Reference

7-16

System Interconnect Master Properties

System Interconnect Master Properties
The system interconnect connects to various slave interfaces through the L3 interconnect and L3 slave
peripheral switch.
Table 7-4: System Interconnect Master Interfaces
TrustZone security:
• Secure: All transactions are marked TrustZone secure
• Nonsecure: All transactions are marked TrustZone non-secure
• Per transaction: Transactions can be marked TrustZone secure or TrustZone non-secure, depending on
the state of the system interconnect master.
Issuance is based on the number of read, write, and total transactions.
The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the
depth is based on W, A, and D channels.
Master Width
L2 64
cache
M0
FPGA 64
-to-
HPS
bridge
DMA 64
EMA 32
C 0/1
USB 32
OTG
0/1
NAN 32
D
(16) Each channel has a dedicated FIFO buffer. This allows the channels to function as independent streams.
Altera Corporation
Clock Switch
L3
mpu_l2_ram_clk
intercon‐
nect
L3
l3_main_clk
intercon‐
nect
L3
l4_main_clk
intercon‐
nect
L3 master
l4_main_clk
peripheral
switch
L3 master
usb_mp_clk
peripheral
switch
L3 master
nand_x_clk
peripheral
switch
TrustZone GPV CDAS
Security Access
Per Yes SSPID
Transac‐
tion
Per Yes SAS
Transac‐
tion
Per No SSPID
Transac‐
tion
Secure No SSPID
Nonsecur No SSPID
e
Nonsecur No SSPID
e
2016.10.28
Issuance FIFO Type
Buffer
Depth (1
6)
7, 12, 19 2, 2, 2, AXI
2, 2
16, 16, 2, 2, 6, AXI
32 6, 2
8, 8, 8 2, 2, 2, AXI
2, 2
16, 16, 2, 2, 2, AXI
32 2, 2
2, 2, 4 2, 2, 2 AH
B
1, 8, 9 2, 2, 2, AXI
2, 2
System Interconnect
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