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Cyclone IV Device Handbook, Volume 1

Cyclone IV Device Handbook,

Volume 1

101 Innovation Drive

San Jose, CA 95134

www.altera.com

CYIV-5V1-2.2

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Summary of Contents for Altera Cyclone IV

Page 1 Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-2.2...
Page 2 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 3: Table Of Contents
High-Speed Transceivers (Cyclone IV GX Devices Only) ........
Page 4 Cyclone IV PLL Hardware Overview ........
Page 5 LVPECL I/O Support in Cyclone IV Devices ..........6–34 Differential SSTL I/O Standard Support in Cyclone IV Devices ......6–35...
Page 6 Contents Differential HSTL I/O Standard Support in Cyclone IV Devices ......6–35 True Differential Output Buffer Feature ........... 6–35 Programmable Pre-Emphasis .
Page 7 Configuring Cyclone IV Devices with Jam STAPL ........
Page 8 Contents Chapter 11. Power Requirements for Cyclone IV Devices External Power Supply Requirements ........... . . 11–1 Hot-Socketing Specifications .
Page 9: Chapter Revision Dates
Chapter Revision Dates The chapters in this document, Cyclone IV Device Handbook,, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Cyclone IV FPGA Device Family Overview Revised: March 2016 Part Number: CYIV-51001-2.0...
Page 10 Chapter Revision Dates Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 11: Additional Information
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 12 A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 13: Section I. Device Core
FPGA in the marketplace. This section includes the following chapters: ■ Chapter 1, Cyclone IV FPGA Device Family Overview ■ Chapter 2, Logic Elements and Logic Array Blocks in Cyclone IV Devices ■ Chapter 3, Memory Blocks in Cyclone IV Devices ■...
Page 14 I–2 Section I: Device Core Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 15: Chapter 1. Cyclone Iv Fpga Device Family Overview
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 16 Flexible clocking structure to support multiple protocols in a single transceiver ■ block ■ Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1: ×1, ×2, and ×4 lane configurations ■ End-point and root-port configurations ■...
Page 17: Device Resources
Up to eight phase-locked loops (PLLs) per device ■ Offered in commercial and industrial temperature grades Device Resources Table 1–1 lists Cyclone IV E device resources. Table 1–1. Resources for the Cyclone IV E Device Family Resources Logic elements (LEs) 6,272 10,320 15,408...
Page 18 1–4 Chapter 1: Cyclone IV FPGA Device Family Overview Device Resources Table 1–2 lists Cyclone IV GX device resources. Table 1–2. Resources for the Cyclone IV GX Device Family Resources Logic elements (LEs) 14,400 21,280 29,440 29,440 49,888 73,920 109,424...
Page 19: Package Matrix
Package Matrix Table 1–3 lists Cyclone IV E device package offerings. (1), Table 1–3. Package Offerings for the Cyclone IV E Device Family Package E144 M164 M256 U256 F256 F324 U484 F484 F780 Size (mm) 22 × 22 8 × 8 9 x 9 14 ×...
Page 20 Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts. Table 1–4. Package Offerings for the Cyclone IV GX Device Family Package F169 F324 F484 F672 F896 Size (mm) 14 × 14 19 × 19 23 × 23 27 ×...
Page 21: Cyclone Iv Device Family Speed Grades
Chapter 1: Cyclone IV FPGA Device Family Overview 1–7 Cyclone IV Device Family Speed Grades Cyclone IV Device Family Speed Grades Table 1–5 lists the Cyclone IV GX devices speed grades. Table 1–5. Speed Grades for the Cyclone IV GX Device Family Device F169 F324 F484 F672...
Page 22: Cyclone Iv Device Family Architecture
Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP including finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions for use with the multiplier blocks.
Page 23: I/O Features
Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces on the top, bottom, and right sides of the device. Cyclone IV E devices also support these interfaces on the left side of the device. Interfaces may span two or more sides of ®...
Page 24: Configuration
The cyclical redundancy check (CRC) error detection feature during user mode is supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only supported for the devices with the core voltage of 1.2 V.
Page 25: Hard Ip For Pci Express (Cyclone Iv Gx Devices Only)
Hard IP for PCI Express (Cyclone IV GX Devices Only) Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE) in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that implements the PHY-MAC layer, Data Link Layer, and Transaction Layer functionality.
Page 26: Reference And Ordering Information
Reference and Ordering Information Reference and Ordering Information Figure 1–2 shows the ordering codes for Cyclone IV GX devices. Figure 1–2. Packaging Ordering Information for the Cyclone IV GX Device Member Code Package Type 15 : 14,400 logic elements F : FineLine BGA (FBGA)
Page 27: Document Revision History
Updated Figure 1–3. ■ Minor text edits. ■ Added Cyclone IV E devices in Table 1–1, Table 1–3, and Table 1–6 for the ■ Quartus II software version 9.1 SP1 release. Added the “Cyclone IV Device Family Speed Grades” and “Configuration”...
Page 28 1–14 Chapter 1: Cyclone IV FPGA Device Family Overview Document Revision History Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 29: Logic Elements
© 2009 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 30: Le Features
2–2 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Logic Elements Figure 2–1 shows the LEs for Cyclone IV devices. Figure 2–1. Cyclone IV Device LEs Register Chain Register Bypass LAB-Wide Routing from Synchronous LAB-Wide previous LE...
Page 31: Le Operating Modes
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–3 LE Operating Modes In addition to the three general routing outputs, LEs in an LAB have register chain outputs, which allows registers in the same LAB to cascade together. The register chain output allows the LUTs to be used for combinational functions and the registers to be used for an unrelated shift register implementation.
Page 32: Arithmetic Mode
2–4 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices LE Operating Modes Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry...
Page 33: Logic Array Blocks
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–5 Logic Array Blocks Logic Array Blocks Logic array blocks (LABs) contain groups of LEs. Topology Each LAB consists of the following features: ■ 16 LEs LAB control signals ■...
Page 34: Lab Interconnects
2–6 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices LAB Control Signals LAB Interconnects The LAB local interconnect is driven by column and row interconnects and LE outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM blocks, and embedded multipliers from the left and right can also drive the local interconnect of a LAB through the direct link connection.
Page 35: Document Revision History
Cyclone IV devices only support either a preset or asynchronous clear signal. In addition to the clear port, Cyclone IV devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin.
Page 36 2–8 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook, November 2009 Altera Corporation Volume 1...
Page 37: Chapter 3. Memory Blocks In Cyclone Iv Devices
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 38 (1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control logic. (2) Width modes of ×32 and ×36 are not available. For information about the number of M9K memory blocks for Cyclone IV devices, refer to the Cyclone IV Device Family Overview chapter in volume 1 of the Cyclone IV Device Handbook.
Page 39: Control Signals
Parity checking for error detection is possible with the parity bit along with internal logic resources. Cyclone IV devices M9K memory blocks support a parity bit for each storage byte. You can use this bit as either a parity bit or as an additional data bit. No parity function is actually performed on this bit.
Page 40: Packed Mode Support
PortA and PortB data widths of the individual M9K memory blocks are multiples of 8 or 9 bits. Packed Mode Support Cyclone IV devices M9K memory blocks support packed mode. You can implement two single-port memory blocks in a single block under the following conditions: ■...
Page 41: Address Clock Enable Support
Overview Address Clock Enable Support Cyclone IV devices M9K memory blocks support an active-low address clock enable, which holds the previous address value for as long as the addressstall signal is high (addressstall = '1'). When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable.
Page 42: Mixed-Width Support
Chapter 3: Memory Blocks in Cyclone IV Devices Overview Figure 3–3 Figure 3–4 show the address clock enable waveform during read and write cycles, respectively. Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform inclock rdaddress rden addressstall latched address...
Page 43: Asynchronous Clear
Memory Modes Cyclone IV devices M9K memory blocks allow you to implement fully-synchronous SRAM memory in multiple modes of operation. Cyclone IV devices M9K memory blocks do not support asynchronous (unregistered) memory inputs. M9K memory blocks support the following modes: Single-port ■...
Page 44: Single-Port Mode
3–8 Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes Violating the setup or hold time on the M9K memory block input registers may corrupt memory contents. This applies to both read and write operations. Single-Port Mode Single-port mode supports non-simultaneous read and write operations from a single address.
Page 45: Simple Dual-Port Mode
Cyclone IV devices M9K memory blocks support mixed-width configurations, allowing different read and write port widths. Table 3–3 lists mixed-width configurations. Table 3–3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2) Write Port Read Port 8192 × 1 4096 ×...
Page 46 3–10 Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes Table 3–3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2) Write Port Read Port 8192 × 1 4096 × 2 2048 × 4 1024 ×...
Page 47: True Dual-Port Mode
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit (18-bit with parity). Table 3–4 lists the possible M9K block mixed-port width configurations. Table 3–4. Cyclone IV Devices M9K Block Mixed-Width Configurations (True Dual-Port Mode) Write Port Read Port 8192 ×...
Page 48: Shift Register Mode
This results in unknown data being stored to that address location. There is no conflict resolution circuitry built into the Cyclone IV devices M9K memory blocks. You must handle address conflicts external to the RAM block.
Page 49: Rom Mode
Shift Register ROM Mode Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the ROM contents of these blocks. The address lines of the ROM are registered. The outputs can be registered or unregistered. The ROM read operation is identical to the read operation in the single-port RAM configuration.
Page 50: Clocking Modes
A and B registers. Input or Output Clock Mode Cyclone IV devices M9K memory blocks can implement input or output clock mode for FIFO, single-port, true, and simple dual-port memories. In this mode, an input clock controls all input registers to the memory block including data, address, byteena, wren, and rden registers.
Page 51: Read Or Write Clock Mode
Design Considerations Read or Write Clock Mode Cyclone IV devices M9K memory blocks can implement read or write clock mode for FIFO and simple dual-port memories. In this mode, a write clock controls the data inputs, write address, and wren registers. Similarly, a read clock controls the data outputs, read address, and rden registers.
Page 52: Same-Port Read-During-Write Mode
3–16 Chapter 3: Memory Blocks in Cyclone IV Devices Design Considerations Same-Port Read-During-Write Mode This mode applies to a single-port RAM or the same port of a true dual-port RAM. In the same port read-during-write mode, there are two output choices: New Data mode (or flow-through) and Old Data mode.
Page 53: Conflict Resolution
Chapter 3: Memory Blocks in Cyclone IV Devices 3–17 Design Considerations In this mode, you also have two output choices: Old Data mode or Don't Care mode. In Old Data mode, a read-during-write operation to different ports causes the RAM outputs to reflect the old data at that address location.
Page 54: Power-Up Conditions And Memory Initialization
Document Revision History Power-Up Conditions and Memory Initialization The M9K memory block outputs of Cyclone IV devices power up to zero (cleared) regardless of whether the output registers are used or bypassed. All M9K memory blocks support initialization using a .mif. You can create .mifs in the Quartus II software and specify their use using the RAM MegaWizard Plug-In Manager when instantiating memory in your design.
Page 55: Embedded Multiplier Block Overview
© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 56: Architecture
(1) These columns show the number of 9 × 9 or 18 × 18 multipliers for each device. In addition to the embedded multipliers in Cyclone IV devices, you can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The LUTs...
Page 57: Input Registers
Chapter 4: Embedded Multipliers in Cyclone IV Devices 4–3 Architecture Figure 4–2 shows the multiplier block architecture. Figure 4–2. Multiplier Block Architecture signa signb aclr clock Data A Data Out CLRN CLRN Data B Output Input Register Register CLRN Embedded Multiplier Block...
Page 58: Output Registers
■ Up to two 9 × 9 independent multipliers You can also use embedded multipliers of Cyclone IV devices to implement multiplier adder and multiplier accumulator functions, in which the multiplier portion of the function is implemented with embedded multipliers, and the adder or accumulator function is implemented in logic elements (LEs).
Page 59: 18-Bit Multipliers
Chapter 4: Embedded Multipliers in Cyclone IV Devices 4–5 Operational Modes 18-Bit Multipliers You can configure each embedded multiplier to support a single 18 × 18 multiplier for input widths of 10 to 18 bits. Figure 4–3 shows the embedded multiplier configured to support an 18-bit multiplier.
Page 60: 9-Bit Multipliers
4–6 Chapter 4: Embedded Multipliers in Cyclone IV Devices Operational Modes 9-Bit Multipliers You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits. Figure 4–4 shows the embedded multiplier configured to support two 9-bit multipliers.
Page 61: Document Revision History
Chapter 4: Embedded Multipliers in Cyclone IV Devices 4–7 Document Revision History Document Revision History Table 4–3 lists the revision history for this chapter. Table 4–3. Document Revision History Date Version Changes Added Cyclone IV E devices in Table 4–1...
Page 62 4–8 Chapter 4: Embedded Multipliers in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook, February 2010 Altera Corporation Volume 1...
Page 63: Clock Networks
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 64: Gclk Network
5–2 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Clock Networks For more information about the number of GCLK networks in each device density, refer to the Cyclone IV FPGA Device Family Overview chapter. GCLK Network GCLKs drive throughout the entire device, feeding all device quadrants. All resources in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks, and M9K memory blocks) can use GCLKs as clock sources.
Page 65 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–3 Clock Networks (1), Table 5–1. GCLK Network Connections for EP4CGX15, EP4CGX22, and EP4CGX30 (Part 2 of 2) GCLK Networks GCLK Network Clock Sources 10 11 12 13 14 15 16 17 18 19 —...
Page 66 (1), Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (Part 1 of 4) GCLK Networks GCLK Network Clock Sources 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 —...
Page 67 (1), Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (Part 2 of 4) GCLK Networks GCLK Network Clock Sources 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 —...
Page 68 (1), Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (Part 3 of 4) GCLK Networks GCLK Network Clock Sources 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 —...
Page 69 (2) PLL_1, PLL_2, PLL_3, and PLL_4 are general purpose PLLs while PLL_5, PLL_6, PLL_7, and PLL_8 are multipurpose PLLs. (3) PLL_7 and PLL_8 are not available in EP4CXGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F484 package. Table 5–3. GCLK Network Connections for Cyclone IV E Devices (Part 1 of 3)
Page 70 Table 5–3. GCLK Network Connections for Cyclone IV E Devices (Part 2 of 3) GCLK Networks GCLK Network Clock Sources 10 11 12 13 14 15 16 17 18 19 CLK15/DIFFCLK_6p — — — — — — — — —...
Page 71 5–3: (1) EP4CE6 and EP4CE10 devices only have GCLK networks 0 to 9. (2) These pins apply to all Cyclone IV E devices except EP4CE6 and EP4CE10 devices. (3) EP4CE6 and EP4CE10 devices only have PLL_1 and PLL_2. (4) This pin applies only to EP4CE6 and EP4CE10 devices.
Page 72: Clock Control Block
Figure 5–3 on page 5–13, and Figure 5–4 on page 5–14. The clock control blocks on the left side of the Cyclone IV GX device do not support any clock inputs. The control block has two functions: ■ Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK , and...
Page 73 (5) You can use internal logic to enable or disable the GCLK in user mode. (6) CLK[ ] is not available on the left side of Cyclone IV E devices. Each PLL generates five clock outputs through the c[4..0] counters. Two of these...
Page 74: Gclk Network Clock Source Generation
5–3, and Figure 5–4 on page 5–14 show the Cyclone IV PLLs, clock inputs, and clock control block location for different Cyclone IV device densities. (1), Figure 5–2. Clock Networks and Clock Control Block Locations in EP4CGX15, EP4CGX22, and EP4CGX30 Devices DPCLK[13..12] (5)
Page 75 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–13 Clock Networks Figure 5–3. Clock Networks and Clock Control Block Locations in EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and (1), EP4CGX150 Devices DPCLK[17..15] DPCLK[14..12] CLKIO[11..8] REFCLK[4,5]p/n (4) PLL_8 PLL_2 PLL_4 Clock...
Page 76 (3) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated. (4) PLL_3 and PLL_4 are not available in EP4CE6 and EP4CE10 devices. The inputs to the clock control blocks on each side of the Cyclone IV GX device must be chosen from among the following clock sources: Four clock input pins ■...
Page 77 EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices can drive six GCLK networks. The inputs to the five clock control blocks on each side of the Cyclone IV E device must be chosen from among the following clock sources: ■...
Page 78: Gclk Network Power Down
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins. GCLK Network Power Down You can disable a Cyclone IV device’s GCLK (power down) using both static and dynamic approaches. In the static approach, configuration bits are set in the configuration file generated by the Quartus II software, which automatically disables unused GCLKs.
Page 79 The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization. Altera recommends using the clkena signals when switching the clock source to the PLLs or the GCLK. The recommended sequence is: 1.
Page 80: Plls In Cyclone Iv Devices
Cyclone IV GX devices contain up to eight general purpose PLLs and multipurpose PLLs while Cyclone IV E devices have up to four general purpose PLLs that provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.
Page 81 (2) This is applicable to all Cyclone IV devices. (3) This is applicable to all Cyclone IV devices except EP4CGX15 devices in all packages, EP4CGX22, and EP4CGX30 devices in F169 package. (4) This is only applicable to EP4CGX15, EP4CGX22, and all EP4CGX30 devices except EP4CGX30 in the F484 package..
Page 82: Cyclone Iv Pll Hardware Overview
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications. (3) The smallest phase shift is determined by the VCO period divided by eight. For degree increments, Cyclone IV E devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
Page 83: External Clock Outputs
Cyclone IV Device Datasheet chapter. External Clock Outputs Each PLL of Cyclone IV devices supports one single-ended clock output or one differential clock output. Only the C0 output counter can feed the dedicated external clock outputs, as shown in Figure 5–11, without going through the GCLK.
Page 84 Cyclone IV Device I/O Features chapter. Cyclone IV PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as GPIO pins if external PLL clocking is not required.
Page 85: Clock Feedback Modes
5–23 Clock Feedback Modes Clock Feedback Modes Cyclone IV PLLs support up to five different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. For the supported feedback modes, refer to Table 5–5 on page 5–18 Cyclone IV GX PLLs and Table 5–6 on page 5–19...
Page 86: No Compensation Mode
5–24 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Clock Feedback Modes No Compensation Mode In no compensation mode, the PLL does not compensate for any clock networks. This provides better jitter performance because clock feedback into the PFD does not pass through as much circuitry.
Page 87: Zero Delay Buffer Mode
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–25 Clock Feedback Modes Figure 5–14 shows a waveform example of the phase relationship of the PLL clocks in this mode. Figure 5–14. Phase Relationship Between PLL Clocks in Normal Mode...
Page 88: Deterministic Latency Compensation Mode
Clock Multiplication and Division Each Cyclone IV PLL provides clock synthesis for PLL output ports using M/(N*post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match f (M/N).
Page 89: Post-Scale Counter Cascading
Hardware Features Post-Scale Counter Cascading PLLs of Cyclone IV devices support post-scale counter cascading to create counters larger than 512. This is implemented by feeding the output of one C counter into the input of the next C counter, as shown in Figure 5–16.
Page 90: Clock Switchover
Automatic Clock Switchover PLLs of Cyclone IV devices support a fully configurable clock switchover capability. When the current reference clock is not present, the clock-sense block automatically switches to the backup clock for PLL reference. The clock switchover circuit also sends out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to...
Page 91: Manual Override
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–29 Hardware Features 20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. Choose the secondary clock frequency so the VCO operates in the recommended frequency range.
Page 92: Manual Clock Switchover
Manual Clock Switchover PLLs of Cyclone IV devices support manual switchover, in which the clkswitch signal controls whether inclk0 or inclk1 is the input clock to the PLL. The characteristics of a manual switchover are similar to the manual override feature in an automatic clock switchover, in which the switchover circuit is edge-sensitive.
Page 93 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–31 Hardware Features ■ When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 20%. However, differences between the two clock sources (frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL ensures that the correct phase relationships are maintained between the input and output clocks.
Page 94: Programmable Bandwidth
You can phase shift the output clocks from the PLLs of Cyclone IV devices in one of two ways: Fine resolution using VCO phase taps ■...
Page 95: Pll Cascading
You can use the coarse and fine phase shifts to implement clock delays in Cyclone IV devices. Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The phase shift is configurable for any number of times. Each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly.
Page 96: Pll Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency synthesis and phase shifts. In PLLs of Cyclone IV devices, you can reconfigure both counter settings and phase shift the PLL output clock in real time. You can also change the charge pump and loop filter components, which dynamically affects PLL bandwidth.
Page 97 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–35 PLL Reconfiguration Figure 5–22 shows how to adjust PLL counter settings dynamically by shifting their new settings into a serial shift register chain or scan chain. Serial data shifts to the scan chain via the scandataport, and shift registers are clocked by scanclk.
Page 98: Post-Scale Counters (C0 To C4)
5–36 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices PLL Reconfiguration Figure 5–23 shows a functional simulation of the PLL reconfiguration feature. Figure 5–23. PLL Reconfiguration Scan Chain scandata D0 (LSB) Dn (MSB) scanclk scanclkena scandataout D0_old Dn_old...
Page 99: Scan Chain Description
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–37 PLL Reconfiguration ■ Low time count = 1 cycle rselodd = 1 effectively equals: ■ High time count = 1.5 cycles ■ Low time count = 1.5 cycles ■...
Page 100: Charge Pump And Loop Filter
5–38 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices PLL Reconfiguration Figure 5–25 shows the scan chain bit order sequence for one PLL post-scale counter in PLLs of Cyclone IV devices. Figure 5–25. Scan Chain Bit Order DATAIN...
Page 101: Bypassing A Pll Counter
Bypassing a PLL counter results in a divide (N, C0 to C4 counters) factor of one. Table 5–11 lists the settings for bypassing the counters in PLLs of Cyclone IV devices. Table 5–11. PLL Counter Settings PLL Scan Chain Bits [0..8] Settings...
Page 102 5–40 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices PLL Reconfiguration Table 5–12. Dynamic Phase Shifting Control Signals (Part 2 of 2) Signal Name Description Source Destination Free running clock from core used in combination with phasestep to enable or...
Page 103: Spread-Spectrum Clocking
Instead, the input signal looks like deterministic jitter at the input of the PLL. PLLs of Cyclone IV devices can track a spread-spectrum input clock as long as it is in the input jitter tolerance specifications and the modulation frequency of the input clock is below the PLL bandwidth, that is specified in the fitter report.
Page 104: Document Revision History
July 2010 Updated Table 5–1, Table 5–2, and Table 5–5. ■ Updated “Clock Feedback Modes” section. ■ Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1 ■ release. Updated “Clock Networks” section. ■ Updated Table 5–1 and Table 5–2.
Page 105: Section Ii. I/O Interfaces
■ Chapter 6, I/O Features in Cyclone IV Devices ■ Chapter 7, External Memory Interfaces in Cyclone IV Devices Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
Page 106 II–2 Section II: I/O Interfaces Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 107 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 108: Cyclone Iv I/O Elements
“Software Overview” on page 6–38 ■ Cyclone IV I/O Elements Cyclone IV I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single-data rate transfer. I/O pins support various single-ended and differential I/O standards.
Page 109: I/O Element Features
(1) Tri-state control is not available for outputs configured with true differential I/O standards. I/O Element Features The Cyclone IV IOE offers a range of programmable features for an I/O pin. These features increase the flexibility of I/O utilization and provide a way to reduce the usage of external discrete components, such as pull-up resistors and diodes.
Page 110: Slew Rate Control
Bus Hold Each Cyclone IV device user I/O pin provides an optional bus-hold feature. The bus-hold circuitry holds the signal on an I/O pin at its last-driven state. Because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated.
Page 111: Programmable Pull-Up Resistor
Cyclone IV Device Datasheet chapter. Programmable Pull-Up Resistor Each Cyclone IV device I/O pin provides an optional programmable pull-up resistor while in user mode. If you enable this feature for an I/O pin, the pull-up resistor holds the output to the V level of the output pin’s bank.
Page 112: Pci-Clamp Diode
2 of the Quartus II Handbook. PCI-Clamp Diode Cyclone IV devices provide an optional PCI-clamp diode enabled input and output for each I/O pin. Dual-purpose configuration pins support the diode in user mode if the specific pins are not used as configuration pins for the selected configuration scheme.
Page 113 Chapter 6: I/O Features in Cyclone IV Devices 6–7 OCT Support Table 6–2 lists the I/O standards that support impedance matching and series termination. Table 6–2. Cyclone IV Device I/O Features Support (Part 1 of 2) OCT with OCT Without IOH/IOL Current Strength Cyclone Cyclone...
Page 114: On-Chip Series Termination With Calibration
(2) The differential SSTL-18 and SSTL-2, differential HSTL-18, HSTL-15, and HSTL-12 I/O standards are supported only on clock input pins and PLL output clock pins. (3) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only for Cyclone IV E devices and right I/O banks 5 and 6 only for Cyclone IV GX devices.
Page 115 OCT with calibration is achieved using the OCT calibration block circuitry. There is one OCT calibration block in each of I/O banks 2, 4, 5, and 7 for Cyclone IV E devices and I/O banks 4, 5, and 7 for Cyclone IV GX devices. Each calibration block supports each side of the I/O banks.
Page 116: On-Chip Series Termination Without Calibration
Cyclone IV devices support driver impedance matching to match the impedance of the transmission line, which is typically 25 or 50 . When used with the output drivers, OCT sets the output driver impedance to 25 or 50 . Cyclone IV devices also = 50 ) for SSTL-2 and SSTL-18.
Page 117: I/O Standards
Cyclone IV devices support 3.3-, 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-V I/O standards. Table 6–3 summarizes I/O standards supported by Cyclone IV devices and which I/O pins support them. Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 1 of 3) Level (in V) Column I/O Pins Row I/O Pins...
Page 118 6–12 Chapter 6: I/O Features in Cyclone IV Devices I/O Standards Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints (Part 2 of 3) Level (in V) Column I/O Pins Row I/O Pins CCIO Standard User I/O Standard Type...
Page 119: Termination Scheme For I/O Standards
(1) Cyclone IV GX devices only support right I/O pins. (2) The PCI-clamp diode must be enabled for 3.3-V/3.0-V LVTTL/LVCMOS. (3) The Cyclone IV architecture supports the MultiVolt I/O interface feature that allows Cyclone IV devices in all packages to interface with I/O systems that have different supply voltages.
Page 120: Voltage-Referenced I/O Standard Termination
). The reference voltage of the receiving device tracks the termination voltage of the transmitting device, as shown in Figure 6–5 Figure 6–6. Figure 6–5. Cyclone IV Devices HSTL I/O Standard Termination HSTL Class I Termination HSTL Class II V TT...
Page 121: Differential I/O Standard Termination
Cyclone IV devices support differential SSTL-2 and SSTL-18, differential HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential LVPECL. Figure 6–7. Cyclone IV Devices Differential HSTL I/O Standard Class I and Class II Interface and Termination Termination Differential HSTL Class I...
Page 122: I/O Banks
Chapter 6: I/O Features in Cyclone IV Devices I/O Banks I/O Banks I/O pins on Cyclone IV devices are grouped together into I/O banks. Each bank has a separate power bus. Cyclone IV E devices have eight I/O banks, as shown in Figure 6–9.
Page 123 Chapter 6: I/O Features in Cyclone IV Devices 6–17 I/O Banks Figure 6–9 shows the overview of Cyclone IV E I/O banks. (1), Figure 6–9. Cyclone IV E I/O Banks I/O Bank 8 I/O Bank 7 All I/O Banks Support: 3.3-V LVTTL/LVCMOS...
Page 124 Chapter 6: I/O Features in Cyclone IV Devices I/O Banks Figure 6–10 Figure 6–11 show the overview of Cyclone IV GX I/O banks. (1), (2), Figure 6–10. Cyclone IV GX I/O Banks for EP4CGX15, EP4CGX22, and EP4CGX30 Configuration pins VCCIO9 VCCIO8 VCC_CLKIN8A VCCIO7...
Page 125 Chapter 6: I/O Features in Cyclone IV Devices 6–19 I/O Banks (1), (2), Figure 6–11. Cyclone IV GX I/O Banks for EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 VCCIO9 VCC_CLKIN8B VCCIO8 VCC_CLKIN8A VCCIO7 Configuration I/O Bank I/O Bank 8B I/O Bank 8...
Page 126 Each Cyclone IV I/O bank has a VREF bus to accommodate voltage-referenced I/O standards. Each VREF pin is the reference source for its V group. If you use a V group for voltage-referenced I/O standards, connect the VREF pin for that group to the appropriate voltage level.
Page 127 Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices (Part 2 of 2) Bank Note to Table 6–4: (1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
Page 128: High-Speed Differential Interfaces
National Semiconductor Corporation. Cyclone IV devices meet the National Semiconductor Corporation PPDS Interface Specification and support the PPDS standard for outputs only. All the I/O banks of Cyclone IV devices support the PPDS standard for output pins only. The LVDS standard does not require an input reference voltage, but it does require a 100-...
Page 129: External Memory Interfacing
6–23 Pad Placement and DC Guidelines External Memory Interfacing Cyclone IV devices support I/O standards required to interface with a broad range of external memory interfaces, such as DDR SDRAM, DDR2 SDRAM, and QDR II SRAM. For more information about Cyclone IV devices external memory interface support,...
Page 130: High-Speed I/O Interface
True output drivers for LVDS, RSDS, mini-LVDS, and PPDS are on the right I/O banks. On the Cyclone IV E row I/O banks and the Cyclone IV GX right I/O banks, some of the differential pin pairs (p and n pins) of the true output drivers are not located on adjacent pins.
Page 131 Table 6–6 Table 6–7 summarize which I/O banks support these I/O standards in the Cyclone IV device family. Table 6–6. Differential I/O Standards Supported in Cyclone IV E I/O Banks External Resistor Differential I/O Standards I/O Bank Location Transmitter (TX)
Page 132 6–26 Chapter 6: I/O Features in Cyclone IV Devices High-Speed I/O Interface Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks External Resistor Differential I/O Standards I/O Bank Location Network at Transmitter (TX) Receiver (RX) Transmitter Not Required...
Page 133 Table 6–8 Table 6–9 summarize the total number of supported row and column differential channels in the Cyclone IV device family. Table 6–8. Cyclone IV E I/O and Differential Channel Count User 179 179 179 179 165 165 165 343...
Page 134: High-Speed I/O Standards Support
Cyclone IV devices. High Speed Serial Interface (HSSI) Input Reference Clock Support Cyclone IV GX devices support the same I/O features for GPIOs with additional new features where current I/O banks 3A and 8A consist of dual-purpose clock input pins...
Page 135: Lvds I/O Standard Support In Cyclone Iv Devices
I/O banks CC_CLKIN8A CC_CLKIN8B to avoid the different power level requirements in the same bank for GPIO. (1), Table 6–10. Cyclone IV GX HSSI REFCLK I/O Standard Support Using GPIO CLKIN Pins VCC_CLKIN Level I/O Pin Type I/O Standard HSSI Protocol...
Page 136: Designing With Lvds
Figure 6–12 shows a point-to-point LVDS interface using Cyclone IV devices true LVDS output and input buffers. Figure 6–12. Cyclone IV Devices LVDS Interface with True Output Buffer on the Right I/O Banks Cyclone IV Device Transmitting Device Receiving Device...
Page 137: Designing With Blvds
Chapter 6: I/O Features in Cyclone IV Devices 6–31 High-Speed I/O Standards Support Figure 6–14 shows a typical BLVDS topology with multiple transmitter and receiver pairs. Figure 6–14. BLVDS Topology with Cyclone IV Devices Transmitters and Receivers 100 kΩ 100 kΩ 50 Ω 50 Ω 50 Ω...
Page 138: Rsds, Mini-Lvds, And Ppds I/O Standard Support In Cyclone Iv Devices
Figure 6–15 shows an RSDS, mini-LVDS, or PPDS interface with a true output buffer. Figure 6–15. Cyclone IV Devices RSDS, Mini-LVDS, or PPDS Interface with True Output Buffer on the Right I/O Banks Cyclone IV Device...
Page 139 50  ------------------- - ------ - Altera recommends that you perform simulations using Cyclone IV devices IBIS models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS requirements. It is possible to use a single external resistor instead of using three resistors in the...
Page 140: Lvpecl I/O Support In Cyclone Iv Devices
Z 0 = 50 Ω 0.1 µF Note to Figure 6–18: (1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA transmitter is used. Figure 6–19 shows the LVPECL DC-coupled termination. Figure 6–19. LVPECL DC-Coupled Termination Cyclone IV Device...
Page 141: Differential Sstl I/O Standard Support In Cyclone Iv Devices
The differential HSTL I/O standard is used for the applications designed to operate in 0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic switching range. Cyclone IV devices support differential HSTL-18, HSTL-15, and HSTL-12 I/O standards. The differential HSTL input standard is available on GCLK pins only, treating the differential inputs as two single-ended HSTL and only decoding one of them.
Page 142: High-Speed I/O Timing
High-Speed I/O Timing This section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in Cyclone IV devices. Timing for source-synchronous signaling is based on skew between the data and clock signals. High-speed differential data transmission requires timing parameters provided by IC vendors and requires you to consider the board skew, cable skew, and clock jitter.
Page 143: Design Guidelines
For more information, refer to the Cyclone IV Device Datasheet chapter. Design Guidelines This section provides guidelines for designing with Cyclone IV devices. Differential Pad Placement Guidelines To maintain an acceptable noise level on the V supply, you must observe some CCIO restrictions on the placement of single-ended I/O pins in relation to differential pads.
Page 144: Board Design Considerations
Software Overview Board Design Considerations This section explains how to achieve the optimal performance from a Cyclone IV I/O interface and ensure first-time success in implementing a functional design with optimal signal quality. You must consider the critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques to get the best performance from Cyclone IV devices.
Page 145: Document Revision History
There is a list of parameters in the ALTLVDS megafunction that you can set to customize your SERDES based on your design requirements. The megafunction is optimized to use Cyclone IV devices resources to create high-speed I/O interfaces in the most effective manner.
Page 146 Document Revision History Table 6–12. Document Revision History (Part 2 of 2) Date Version Changes Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1 ■ release. Updated Table 6–2, Table 6–3, and Table 6–10. ■...
Page 147: Chapter 7. External Memory Interfaces In Cyclone Iv Devices
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 148: Cyclone Iv Devices Memory Interfaces Pin Support
External Memory Interface Handbook. Data and Data Clock/Strobe Pins Cyclone IV data pins for external memory interfaces are called D for write data, Q for read data, or DQ for shared read and write data pins. The read-data strobes or read clocks are called DQS pins.
Page 149 All I/O banks in Cyclone IV devices can support DQ and DQS signals with DQ-bus modes of ×8, ×9, ×16, ×18, ×32, and ×36 except Cyclone IV GX devices that do not support left I/O bank interface. DDR2 and DDR SDRAM interfaces use ×8 mode DQS group regardless of the interface width.
Page 150 Table 7–1 lists the number of DQS or DQ groups supported on each side of the Cyclone IV GX device. Table 7–1. Cyclone IV GX Device DQS and DQ Bus Mode Support for Each Side of the Device Number Number...
Page 151 DQS or DQ groups supported on each side of the Cyclone IV E device. Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 3) Number...
Page 152 Chapter 7: External Memory Interfaces in Cyclone IV Devices Cyclone IV Devices Memory Interfaces Pin Support Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 2 of 3) Number Number...
Page 153 Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–7 Cyclone IV Devices Memory Interfaces Pin Support Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 3 of 3) Number Number...
Page 154 Note to Figure 7–2: (1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone IV GX devices except devices in 169-pin FBGA and 324-pin FBGA. Cyclone IV Device Handbook, March 2016 Altera Corporation...
Page 155 DQS, DQ, or CQ# pins in I/O banks of the Cyclone IV GX device in the 324-pin FBGA package only. Figure 7–3. DQS, CQ, or CQ# Pins for Cyclone IV GX Devices in the 324-Pin FBGA Package I/O Bank 9...
Page 156 I/O Bank 4 Note to Figure 7–5: (1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone IV E devices except devices in 144-pin EQFP. Cyclone IV Device Handbook, March 2016 Altera Corporation...
Page 157: Optional Parity, Dm, And Error Correction Coding Pins
I/O Bank 4 In Cyclone IV devices, the ×9 mode uses the same DQ and DQS pins as the ×8 mode, and one additional DQ pin that serves as a regular I/O pin in the ×8 mode. The ×18 mode uses the same DQ and DQS pins as ×16 mode, with two additional DQ pins that serve as...
Page 158: Address And Control/Command Pins
The address signals and the control or command signals are typically sent at a single data rate. You can use any of the user I/O pins on all I/O banks of Cyclone IV devices to generate the address and control or command signals to the memory device.
Page 159 Because the read-capture clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used during read operation in Cyclone IV devices; hence, postamble is not a concern in this case.
Page 160: Ddr Output Registers
A dedicated write DDIO block is implemented in the DDR output and output enable paths. Figure 7–8 shows how a Cyclone IV dedicated write DDIO block is implemented in the I/O element (IOE) registers. Figure 7–8. Cyclone IV Dedicated Write DDIO...
Page 161: Oct With Calibration
OCT calibration block to calibrate one type of termination with the same V CCIO that given side. For more information about the Cyclone IV devices OCT calibration block, refer to the Cyclone IV Device I/O Features chapter. When interfacing with external memory, the PLL is used to generate the memory system clock, the write clock, the capture clock and the logic-core clock.
Page 162: Document Revision History
Updated Table 7–2. ■ Minor text edits. ■ November 2010 Updated “Data and Data Clock/Strobe Pins” section. Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1 ■ release. Updated Table 7–1. ■ February 2010 Added Table 7–2.
Page 163: Section Iii. System Integration
Section III. System Integration This section includes the following chapters: ■ Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices ■ Chapter 9, SEU Mitigation in Cyclone IV Devices ■ Chapter 10, JTAG Boundary-Scan Testing for Cyclone IV Devices ■...
Page 164 III–2 Section III: System Integration Cyclone IV Device Handbook, March 2016 Altera Corporation Volume 1...
Page 165: Configuration
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 166: Configuration Features
Cyclone IV device. The time required by a Cyclone IV device to decompress a configuration file is less than the time required to send the configuration data to the device.
Page 167: Configuration Requirement
Configuration device list. 4. Under Input files to convert, select SOF Data. 5. Click Add File to browse to the Cyclone IV device SRAM object files (.sof). 6. In the Convert Programming Files dialog box, select the .pof you added to SOF Data and click Properties.
Page 168: Power-On Reset (Por) Circuit
To calculate the amount of storage space required for multiple device configurations, add the file size of each device together. Table 8–2. Uncompressed Raw Binary File (.rbf) Sizes for Cyclone IV Devices (Part 1 of 2) Device Data Size (bits)
Page 169: Configuration And Jtag Pin I/O Requirements
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–5 Configuration Table 8–2. Uncompressed Raw Binary File (.rbf) Sizes for Cyclone IV Devices (Part 2 of 2) Device Data Size (bits) EP4CGX15 3,805,568 EP4CGX22 7,600,040 7,600,040 EP4CGX30 22,010,888...
Page 170: Configuration Process
POR. Reset After power up, Cyclone IV devices go through POR. POR delay depends on the MSEL pin settings, which correspond to your configuration scheme. During POR, the device resets, holds nSTATUS and CONF_DONE low, and tri-states all user I/O pins (for PS and FPP configuration schemes only).
Page 171: Configuration Error
You can begin reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin must be low for at least 500 ns. When nCONFIG is pulled low, the Cyclone IV device is reset. The Cyclone IV device also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Page 172: Configuration Scheme
GND without pull-up or pull-down resistors to avoid problems detecting an incorrect configuration scheme. Do not drive the MSEL pins with a microprocessor or another device. Table 8–3. Configuration Schemes for Cyclone IV GX Devices (EP4CGX15, EP4CGX22, and EP4CGX30 [except for F484 Package]) Configuration Scheme...
Page 173 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–9 Configuration Table 8–4. Configuration Schemes for Cyclone IV GX Devices (EP4CGX30 [only for F484 package], EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150) (Part 2 of 2) Configuration Scheme MSEL3 MSEL2 MSEL1 MSEL0...
Page 174: As Configuration (Serial Configuration Devices)
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration For Cyclone IV E devices, the Quartus II software prohibits you from using the LVDS I/O standard in I/O Bank 1 when the configuration device I/O voltage is not 2.5 V. If you need to assign LVDS I/O standard in I/O Bank 1, navigate to Assignments>Device>Settings>Device and Pin Option>Configuration to change...
Page 175 (6) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in AP and FPP modes. (7) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
Page 176 The internal oscillator is designed to ensure that its maximum frequency is guaranteed to meet EPCS device specifications. Cyclone IV devices offer the option to select CLKUSR as the external clock source for DCLK. You can change the clock source option in the Quartus II software in the Configuration tab of the Device and Pin Options dialog box.
Page 177: Multi-Device As Configuration
(3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device. (4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone IV device in AS mode and the slave devices in PS mode.
Page 178: Configuring Multiple Cyclone Iv Devices With The Same Design
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration The first Cyclone IV device in the chain is the configuration master and it controls the configuration of the entire chain. Other Altera devices that support PS configuration can also be part of the chain as configuration slaves.
Page 179 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–15 Configuration four devices. During the first configuration cycle, the master device reads its configuration data from the serial configuration device while holding nCEO high. After completing its configuration cycle, the master device drives nCE low and sends the second copy of the configuration data to all three slave devices, configuring them simultaneously.
Page 180 FPP modes. (9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK. (10) For multi-devices AS configuration using Cyclone IV E with 1,0 V core voltage, the maximum board trace-length from the serial configuration device to the junction-split on both DCLK and Data0 line is 3.5 inches.
Page 181 (2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device. (3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone IV device in AS mode and the slave devices in PS mode.
Page 182 Table 8–7: (1) For multi-devices AS configuration using Cyclone IV E with 1,0 V core voltage, the maximum board trace-length from the serial configuration device to the junction-split on both DCLK and Data0 line is 3.5 inches. Estimating AS Configuration Time AS configuration time is dominated by the time it takes to transfer data from the serial configuration device to the Cyclone IV device.
Page 183: Programming Serial Configuration Devices
Altera has developed the Serial FlashLoader (SFL), a JTAG-based in-system programming solution for Altera serial configuration devices. The SFL is a bridge design for the Cyclone IV device that uses its JTAG interface to access the EPCS JIC (JTAG Indirect Configuration Device Programming) file and then uses the AS interface to program the EPCS device.
Page 184 GND. (5) The diodes and capacitors must be placed as close as possible to the Cyclone IV device. You must ensure that the diodes and capacitors maintain a maximum AC voltage of 4.1 V. The external diodes and capacitors are required to prevent damage to the Cyclone IV device AS configuration input pins due to possible overshoot when programming the serial configuration device with a download cable.
Page 185: Ap Configuration (Supported Flash Memories)
The speed up in configuration time is mainly due to the 16-bit wide parallel data bus, which is used to retrieve data from the flash memory. Some of the smaller Cyclone IV E devices or package options do not support the AP configuration scheme.
Page 186: Ap Configuration Supported Flash Memories
AP Configuration Supported Flash Memories The AP configuration controller in Cyclone IV E devices is designed to interface with two industry-standard flash families—the Micron P30 Parallel NOR flash family and the Micron P33 Parallel NOR flash family. Unlike serial configuration devices, both of the flash families supported in AP configuration scheme are designed to interface with microprocessors.
Page 187: Single-Device Ap Configuration
The supported parallel flash memories output a control signal (WAIT) to Cyclone IV E devices to indicate when synchronous data is ready on the data bus. Cyclone IV E devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the flash memory.
Page 188 I/O CCIO banks 1, 6, 7, and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the level shifter between the Micron P30 or P33 flash and the Cyclone IV E device in the AP configuration scheme.
Page 189: Multi-Device Ap Configuration
2.5-, 3.0-, and 3.3-V AP configuration option. However, if there are any other devices sharing the same flash I/Os with Cyclone IV E devices, all shared pins are still subject to the 4.1-V limit and may require series resistors.
Page 190: Byte-Wide Multi-Device Ap Configuration
I/O to monitor the WAIT signal from the Micron P30 or P33 flash. (6) Connect the repeater buffers between the Cyclone IV E master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V.
Page 191 I/O pin to monitor the WAIT signal from the Micron P30 or P33 flash. (6) Connect the repeater buffers between the Cyclone IV E master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V.
Page 192: Guidelines For Connecting Parallel Flash To Cyclone Iv E Devices For An Ap Interface
Cyclone IV E device and override the weak 10-k pull-down resistor on the nCE pin. This resets the master Cyclone IV E device and causes it to tri-state its AP configuration bus. The other master device then takes control of the AP configuration bus.
Page 193 I/O to monitor the WAIT signal from the Micron P30 or P33 flash. (5) When cascading Cyclone IV E devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices for DATA[15..0] and DCLK.
Page 194: Estimating Ap Configuration Time
Table 8–11 on page 8–28. (2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize reflection noise from the transmission line. The M length is applicable for this setup. Estimating AP Configuration Time AP configuration time is dominated by the time it takes to transfer data from the parallel flash to Cyclone IV E devices.
Page 195: Programming Parallel Flash Memories
The board intelligent host or download cable uses the four JTAG pins on Cyclone IV E devices to program the parallel flash in system, even if the host or download cable cannot access the configuration pins of the parallel flash.
Page 196: Ps Configuration
II device, microprocessor with flash memory, or a download cable. In the PS scheme, an external host controls the configuration. Configuration data is clocked into the target Cyclone IV device through DATA[0] at each rising edge of DCLK. If your system already contains a common flash interface (CFI) flash memory, you can use it for Cyclone IV device configuration storage as well.
Page 197: Ps Configuration Using An External Host
In the PS configuration scheme, you can use an intelligent host such as a MAX II device or microprocessor that controls the transfer of configuration data from a storage device, such as flash memory, to the target Cyclone IV device. You can store the configuration data in .rbf, .hex, or .ttf format.
Page 198 8–34 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration To ensure DCLK and DATA[0] are not left floating at the end of configuration, the MAX II device must drive them either high or low, whichever is convenient on your board.
Page 199 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–35 Configuration After the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the nCE pin of the second device, which prompts the second device to begin configuration.
Page 200: Ps Configuration Timing
(4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more convenient. When using the AS configuration scheme, DCLK is a Cyclone IV device output pin and must not be driven externally.
Page 201: Ps Configuration Using A Download Cable
Table 8–12: (1) Applicable for Cyclone IV GX and Cyclone IV E devices with 1.2-V core voltage. (2) Applicable for Cyclone IV E devices with 1.0-V core voltage. (3) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
Page 202 8–38 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration The programming hardware or download cable then places the configuration data one bit at a time on the DATA[0] pin of the device. The configuration data is clocked into the target device until CONF_DONE goes high.
Page 203 8–39 Configuration You can use a download cable to configure multiple Cyclone IV device configuration pins. nCONFIG, nSTATUS, DCLK, DATA[0], and CONF_DONE are connected to every device in the chain. All devices in the chain utilize and enter user mode at the same time because all CONF_DONE pins are tied together.
Page 204: Fpp Configuration
MAX II device or microprocessor with flash memory. If your system already contains a CFI flash memory, you can use it for the Cyclone IV device configuration storage as well. The MAX II PFL feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the Cyclone IV device.
Page 205 DATA[7..0]pins. Cyclone IV devices receive configuration data on the DATA[7..0] pins and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Page 206 8–42 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration To ensure that DCLK and DATA[0] are not left floating at the end of the configuration, the MAX II device must drive them either high or low, whichever is convenient on your board.
Page 207 Equation 8–1 on page 8–5. You can use a single configuration chain to configure Cyclone IV devices with other Altera devices that support FPP configuration. To ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device starts reconfiguration in all devices, tie all the CONF_DONE and nSTATUS pins together.
Page 208: Fpp Configuration Timing
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power up, the Cyclone IV device holds nSTATUS low during POR delay. (3) After power up, before and during configuration, CONF_DONE is low.
Page 209: Jtag Configuration
Table 8–13: (1) Applicable for Cyclone IV GX and Cyclone IV E with 1.2-V core voltage. (2) Applicable for Cyclone IV E with 1.0-V core voltage. (3) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
Page 210 For example, if you attempt JTAG configuration in Cyclone IV devices during PS configuration, PS configuration terminates and JTAG configuration begins. If the MSEL pins are set to AS mode, the Cyclone IV device does not output a DCLK signal when JTAG configuration takes place.
Page 211 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–47 Configuration For device using V of 2.5, 3.0, and 3.3 V, refer to Figure 8–23. All I/O inputs must CCIO maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using V of 2.5, 3.0, and...
Page 212 8–48 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration Figure 8–24. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V CCIO Powering the JTAG Pins) CCIO CCIO CCIO 10 kΩ CCIO...
Page 213 Description On all Cyclone IV devices in the chain, nCE must be driven low by connecting it to GND, pulling it low through a resistor, or driving it by some control circuitry. For devices that are also in multi-device AS, AP, PS, or FPP configuration chains, you must connect the nCE pins to GND during JTAG configuration or JTAG configured in the same order as the configuration chain.
Page 214 The number of devices in the JTAG chain is limited only by the drive capability of the download cable. When four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer.
Page 215 (6) Resistor value can vary from 1 k to 10 k. If a non-Cyclone IV device is cascaded in the JTAG-chain, TDO of the non-Cyclone IV device driving into TDI of the Cyclone IV device must fit the maximum overshoot outlined in Equation 8–1 on page...
Page 216: Configuring Cyclone Iv Devices With Jam Stapl
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration JTAG configuration allows an unlimited number of Cyclone IV devices to be cascaded in a JTAG chain. For more information about configuring multiple Altera devices in the same...
Page 217: Combining Jtag And As Configuration Schemes
8–28). This setup uses two 10-pin download cable headers on the board. One download cable is used in JTAG mode to configure the Cyclone IV device directly through the JTAG interface. The other download cable is used in AS mode to program the serial configuration device in-system through the AS programming interface.
Page 218 DATA[1] pin in AP and FPP modes. (8) Resistor value can vary from 1 k to 10 k.. (9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
Page 219: Programming Serial Configuration Devices In-System With The Jtag Interface
The intelligent host or download cable of the board can use the four JTAG pins on the Cyclone IV device to program the serial configuration device in system, even if the host or download cable cannot access the configuration pins (DCLK, DATA, ASDI, and nCS pins).
Page 220 DATA[1] pin in AP and FPP modes. (9) Resistor value can vary from 1 k to 10 k. (10) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
Page 221: Jtag Instructions
PULSE_NCONFIG JTAG instruction to initialize the reconfiguration process. During reconfiguration, the master device is reset and the SFL design no longer exists in the Cyclone IV device and the serial configuration device configures all the devices in the chain with the user design.
Page 222 8–58 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration Use the ACTIVE_DISENGAGE instruction with the CONFIG_IO instruction to interrupt configuration. Table 8–16 lists the sequence of instructions to use for various CONFIG_IO usage scenarios. Table 8–16. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows...
Page 223 The ACTIVE_DISENGAGE instruction is required before JTAG programming regardless of the current state of the Cyclone IV device if the MSEL pins are set to an AS or AP configuration scheme. If the ACTIVE_DISENGAGE instruction is issued during a passive configuration scheme (PS or FPP), it has no effect on the Cyclone IV device.
Page 224 PS or FPP configuration schemes. The nCONFIG pin is disabled when the ACTIVE_ENGAGE instruction is issued. Altera does not recommend using the ACTIVE_ENGAGE instruction, but it is provided as a fail-safe instruction for re-engaging the active configuration controller (AS and AP).
Page 225 CLKUSR pin for 10 clock cycles. Changing the Start Boot Address of the AP Flash In the AP configuration scheme (for Cyclone IV E devices only), you can change the default configuration boot address of the parallel flash memory to any desired address using the APFC_BOOT_ADDR JTAG instruction.
Page 226: Device Configuration Pins
To set these pins to different settings, turn off the Enable input tri-state on active configuration pins in user mode option and set the desired setting from the Dual-purpose Pins Setting menu. Table 8–19. Configuration Pin Summary for Cyclone IV E Devices (Part 1 of 3) Bank...
Page 227 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–63 Configuration Table 8–19. Configuration Pin Summary for Cyclone IV E Devices (Part 2 of 3) Bank Description Input/Output Dedicated Powered By Configuration Mode Input PS, FPP, AS CCIO (1), —...
Page 228 Dual-purpose Pins Setting menu. (3) The CRC_ERROR pin is not available in Cyclone IV E devices with 1.0-V core voltage. (4) The CRC_ERROR pin is a dedicated open-drain output or an optional user I/O pin. Active high signal indicates that the error detection circuit has detected errors in the configuration SRAM bits.
Page 229 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–65 Configuration Table 8–20. Dedicated Configuration Pins on the Cyclone IV Device (Part 2 of 4) Configuration Pin Name User Mode Pin Type Description Scheme Status output—the target Cyclone IV device drives the ■...
Page 230 8–66 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration Table 8–20. Dedicated Configuration Pins on the Cyclone IV Device (Part 3 of 4) Configuration Pin Name User Mode Pin Type Description Scheme Input (PS, In PS and FPP configuration, DCLK is the clock input used...
Page 231 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–67 Configuration Table 8–20. Dedicated Configuration Pins on the Cyclone IV Device (Part 4 of 4) Configuration Pin Name User Mode Pin Type Description Scheme In an AS or PS configuration scheme, DATA[7..2] function as user I/O pins during configuration, which means they are tri-stated.
Page 232 N/A if option is on. Input CLKUSR In AS configuration for Cyclone IV GX devices, you can use this I/O if option is off. pin as an external clock source to generate the DCLK by changing the clock source option in the Quartus II software in the Configuration tab of the Device and Pin Options dialog box.
Page 233: Remote System Upgrade
The remote system upgrade process of the Cyclone IV device consists of the following steps: 1. A Nios II processor (or user logic) implemented in the Cyclone IV device logic array receives new configuration data from a remote location. The connection to...
Page 234: Enabling Remote Update
Enabling Remote Update You can enable or disable remote update for Cyclone IV devices in the Quartus II software before design compilation (in the Compiler Settings menu). To enable remote update in the compiler settings of the project, perform the following steps: 1.
Page 235: Remote System Upgrade Mode
This image is stored in non-volatile memory and is never updated or modified using remote access. When you use the AP configuration in Cyclone IV E devices, the Cyclone IV E device loads the default factory configuration located at the following address after device power-up in remote update mode: boot_address[23:0] = 24'h010000 = 24'b1 0000 0000 0000 0000.
Page 236 ■ A configuration reset (logic array nCONFIG signal or external nCONFIG pin assertion) The Cyclone IV device automatically loads the factory configuration when an error occurs. This user-designed factory configuration reads the remote system upgrade status register to determine the reason for reconfiguration. Then the factory...
Page 237 In user mode, the soft logic (the Nios II processor or state machine and the remote communication interface) assists the Cyclone IV device in determining when a remote system update is arriving. When a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device and triggers the device to load the factory configuration.
Page 238: Dedicated Remote System Upgrade Circuitry
Remote System Upgrade Dedicated Remote System Upgrade Circuitry This section describes the implementation of the Cyclone IV device remote system upgrade dedicated circuitry. The remote system upgrade circuitry is implemented in hard logic. This dedicated circuitry interfaces with the user-defined factory application configurations implemented in the Cyclone IV device logic array to provide the complete remote configuration solution.
Page 239: Remote System Upgrade Registers
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–75 Remote System Upgrade Remote System Upgrade Registers The remote system upgrade block contains a series of registers that stores the configuration addresses, watchdog timer settings, and status information.
Page 240 8–76 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Remote System Upgrade Figure 8–34 shows the control register bit positions. Table 8–23 defines the control register bit contents. The numbers in Figure 8–34 show the bit position of a setting in a register.
Page 241 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–77 Remote System Upgrade ■ External configuration reset (nCONFIG) assertion User watchdog timer time out ■ Table 8–24 lists the contents of the current state logic in the status register, when the...
Page 242: Remote System Upgrade State Machine
8–78 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Remote System Upgrade Table 8–25 lists the contents of previous state register 1 and previous state register 2 in the status register. The status register bit in Table 8–25 shows the bit positions in a 3-bit register.
Page 243: User Watchdog Timer
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–79 Remote System Upgrade The remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition, but before the factory configuration is loaded.
Page 244: Quartus Ii Software Support
Quartus II Software Support Implementation in your design requires a remote system upgrade interface between the Cyclone IV device logic array and remote system upgrade circuitry. You must also generate configuration files for production and remote programming of the system configuration memory.
Page 245 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices 8–81 Document Revision History Table 8–28. Document Revision History (Part 2 of 2) Date Version Changes Updated for the Quartus II software 10.0 release: Updated “Power-On Reset (POR) Circuit”, “Configuration and JTAG Pin I/O ■...
Page 246 8–82 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook, May 2013 Altera Corporation Volume 1...
Page 247: Chapter 9. Seu Mitigation In Cyclone Iv Devices
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 248: User Mode Error Detection
“User Mode Error Detection”. User Mode Error Detection User mode error detection is available in Cyclone IV GX and Cyclone IV E devices with 1.2-V core voltage. Cyclone IV E devices with 1.0-V core voltage do not support user mode error detection.
Page 249: Automated Seu Detection
SEU. You can implement the error detection CRC feature with existing circuitry in Cyclone IV devices, eliminating the need for external logic. The CRC is computed by the device during configuration and checked against an automatically computed CRC during normal operation.
Page 250: Error Detection Block
9–4 Chapter 9: SEU Mitigation in Cyclone IV Devices Error Detection Block WYSIWYG is an optimization technique that performs optimization on a VQM (Verilog Quartus Mapping) netlist in the Quartus II software. Error Detection Block Table 9–3 lists the types of CRC detection to check the configuration bits.
Page 251: Error Detection Timing
The error detection circuitry runs off an internal configuration oscillator with a divisor that sets the maximum frequency. Table 9–5 lists the minimum and maximum error detection frequencies. Table 9–5. Minimum and Maximum Error Detection Frequencies for Cyclone IV Devices Error Detection Maximum Error Minimum Error...
Page 252: Software Support
CRC_ERROR output to the optional dual purpose CRC_ERROR pin. To enable the error detection feature using CRC, perform the following steps: 1. Open the Quartus II software and load a project using Cyclone IV devices. 2. On the Assignments menu, click Settings. The Settings dialog box appears.
Page 253: Accessing Error Detection Block Through User Logic
Chapter 9: SEU Mitigation in Cyclone IV Devices 9–7 Software Support The divisor value divides the frequency of the configuration oscillator output clock. This output clock is used as the clock source for the error detection process. 8. Click OK.
Page 254 9–8 Chapter 9: SEU Mitigation in Cyclone IV Devices Software Support Figure 9–3 shows the error detection block diagram in FPGA devices and shows the interface that the WYSIWYG atom enables in your design. Figure 9–3. Error Detection Block Diagram...
Page 255: Recovering From Crc Errors
31 cycles to read out the 32 bits of the shift register. Recovering from CRC Errors The system that the Altera FPGA resides in must control device reconfiguration. After detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the system to perform the reconfiguration at a time when it is safe for the system to reconfigure the FPGA.
Page 256: Document Revision History
9–10 Chapter 9: SEU Mitigation in Cyclone IV Devices Document Revision History Document Revision History Table 9–8 lists the revision history for this chapter. Table 9–8. Document Revision History Date Version Changes May 2013 Updated “CRC_ERROR Pin Type” in Table 9–2.
Page 257: Chapter 10. Jtag Boundary-Scan Testing For Cyclone Iv Devices
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 258: Ieee Std. 1149.6 Boundary-Scan Register
(GXB_RX[p,n]) in Cyclone IV GX devices are different from the BSCs for I/O pins. Figure 10–1 shows the Cyclone IV GX HSSI transmitter boundary-scan cell. Figure 10–1. HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Cyclone IV GX Devices BSCAN SDOUT...
Page 259: Bst Operation Control
Chapter 10: JTAG Boundary-Scan Testing for Cyclone IV Devices 10–3 BST Operation Control Figure 10–2 shows the Cyclone IV GX HSSI receiver BSC. Figure 10–2. HSSI Receiver BSC with IEEE Std. 1149.6 BST Circuitry for the Cyclone IV GX Devices BSCAN SDOUT BSRX1 AC JTAG Test...
Page 260 10–4 Chapter 10: JTAG Boundary-Scan Testing for Cyclone IV Devices BST Operation Control Table 10–1. Boundary-Scan Register Length for Cyclone IV Devices (Part 2 of 2) Device Boundary-Scan Register Length EP4CGX75 1006 EP4CGX110 1495 EP4CGX150 1495 Note to Table 10–1: (1) For the F484 package of the EP4CGX30 device, the boundary-scan register length is 1006.
Page 261: Extest_Pulse
TCK. The TDO output pin and all JTAG input pins are powered by the V power CCIO supply of I/O Banks (I/O Bank 9 for Cyclone IV GX devices and I/O Bank 1 for Cyclone IV E devices). A JTAG chain can contain several different devices. However, you must use caution if the chain contains devices that have different V levels.
Page 262: Boundary-Scan Description Language Support
You can also generate BSDL files (pre-configuration and post-configuration) for ® IEEE Std. 1149.1/IEEE Std. 1149.6-compliant Cyclone IV devices with the Quartus software version 9.1 SP1 and later. For more information about the procedure to generate BSDL files using the Quartus II software, refer to...
Page 263: Document Revision History
Updated the “BST Operation Control” section. ■ November 2011 Updated Table 10–2. ■ Added Cyclone IV E devices in Table 10–1 and Table 10–2 for the Quartus II ■ software version 9.1 SP1 release. February 2010 Updated Figure 10–1 and Figure 10–2.
Page 264 10–8 Chapter 10: JTAG Boundary-Scan Testing for Cyclone IV Devices Document Revision History Cyclone IV Device Handbook, December 2013 Altera Corporation Volume 1...
Page 265: External Power Supply Requirements
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 266: Hot-Socketing Specifications
11–2 Chapter 11: Power Requirements for Cyclone IV Devices Hot-Socketing Specifications Table 11–1. Power Supply Descriptions for the Cyclone IV GX Devices (Part 2 of 2) Power Supply Pin Nominal Voltage Level (V) Description Transceiver PMA and auxiliary power supply...
Page 267: Hot-Socketing Feature Implementation
Altera device. Power-On Reset Circuitry Cyclone IV devices contain POR circuitry to keep the device in a reset state until the power supply voltage levels have stabilized during power up. During POR, all user I/O pins are tri-stated until the power supplies reach the recommended operating levels.
Page 268: Document Revision History
Document Revision History In some applications, it is necessary for a device to wake up very quickly to begin operation. Cyclone IV devices offer the Fast-On feature to support fast wake-up time applications. The MSEL pin settings determine the POR time (t ) of the device.
Page 269 Cyclone IV Device Handbook, Volume 2 Cyclone IV Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V2-1.9...
Page 270 © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 271 How to Contact Altera ........
Page 272 Document Revision History ............. 1–93 Chapter 2. Cyclone IV Reset Control and Power Down User Reset and Power-Down Signals .
Page 273 Document Revision History ............. 2–24 Chapter 3. Cyclone IV Dynamic Reconfiguration Glossary of Terms .
Page 274 Contents Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2...
Page 275: Chapter Revision Dates
Chapter Revision Dates The chapters in this document, Cyclone IV Device Handbook, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Cyclone IV Transceivers Architecture Revised: February 2015 Part Number: CYIV-52001-3.7...
Page 276 Chapter Revision Dates Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2...
Page 277: Additional Information
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 278 A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2...
Page 279: Section I. Transceivers
This section includes the following chapters: Chapter 1, Cyclone IV Transceivers Architecture ■ ■ Chapter 2, Cyclone IV Reset Control and Power Down ■ Chapter 3, Cyclone IV Dynamic Reconfiguration Revision History Refer to the chapter for its own specific revision history. For information about when the chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
Page 280 I–2 Section I: Transceivers Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2...
Page 281 © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 282 Figure 1–1 Figure 1–2 show the die-top view of the transceiver block and related resource locations in Cyclone IV GX devices. Figure 1–1. F324 and Smaller Packages with Transceiver Channels for Cyclone IV GX Devices F324 and smaller MPLL_2 packages...
Page 283: Chapter 1. Cyclone Iv Transceivers Architecture Transceiver Architecture
Chapter 1: Cyclone IV Transceivers Architecture 1–3 Transceiver Architecture Figure 1–2. F484 and Larger Packages with Transceiver Channels for Cyclone IV GX Devices F484 and larger MPLL_8 GPLL_2 packages Channel 3 Channel 2 Transceiver Not applicable in Block GXBL1 F484 package...
Page 284: Architectural Overview
Chapter 1: Cyclone IV Transceivers Architecture Architectural Overview Architectural Overview Figure 1–3 shows the Cyclone IV GX transceiver channel datapath. Figure 1–3. Transceiver Channel Datapath for Cyclone IV GX Devices Transmitter Channel PCS Transmitter Channel PMA FPGA Fabric Tx Phase...
Page 285: Transmitter Channel Datapath
Chapter 1: Cyclone IV Transceivers Architecture 1–5 Transmitter Channel Datapath Transmitter Channel Datapath The following sections describe the Cyclone IV GX transmitter channel datapath architecture as shown in Figure 1–3: TX Phase Compensation FIFO ■ Byte Serializer ■ 8B/10B Encoder ■...
Page 286: 8B/10B Encoder
Dx.y code, depending on the value entered. It is possible for a downstream 8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting any code error flags. Altera recommends not to assert tx_ctrlenable port for unsupported 8-bit characters.
Page 287 Chapter 1: Cyclone IV Transceivers Architecture 1–7 Transmitter Channel Datapath The following describes the 8B/10B encoder behavior in reset condition (as shown in Figure 1–7): During reset, the 8B/10B encoder ignores the inputs (tx_datain and ■ tx_ctrlenable ports) from the FPGA fabric and outputs the K28.5 pattern from the RD- column continuously until the tx_digitalreset port is deasserted.
Page 288: Miscellaneous Transmitter Pcs Features
1–8 Chapter 1: Cyclone IV Transceivers Architecture Transmitter Channel Datapath at time n + 2 is encoded as a positive disparity code group. In the same example, the current running disparity at time n + 5 indicates that the K28.5 in time n + 6 should be encoded with a positive disparity.
Page 289: Serializer
Chapter 1: Cyclone IV Transceivers Architecture 1–9 Transmitter Channel Datapath ■ Bit reversal—reverses the transmit bit order from LSB-to-MSB (default) to MSB-to-LSB at the input to the serializer. For example, input data to serializer D[7..0] is rewired to D[0..7] for 8-bit data width, and D[9..0] is rewired to D[0..9] for 10-bit data width.
Page 290: Transmitter Output Buffer
Express (PIPE) Mode” on page 1–52. The Cyclone IV GX transmitter output buffers support the 1.5-V PCML I/O standard and are powered by VCCH_GXB power pins with 2.5-V supply. The 2.5-V supply on VCCH_GXB pins are regulated internally to 1.5-V for the transmitter output buffers. The transmitter output buffers support the following additional features: ■...
Page 291: Receiver Channel Datapath
“RX Phase Compensation FIFO” on page 1–25 ■ Receiver Input Buffer Table 1–2 lists the electrical features supported by the Cyclone IV GX receiver input buffer. Table 1–2. Electrical Features Supported by the Receiver Input Buffer Programmable Common I/O Standard...
Page 292 1–12 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath The high-speed serial link can be AC- or DC-coupled, depending on the serial protocol implementation. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter DC common mode voltage as shown in Figure 1–12.
Page 293 Chapter 1: Cyclone IV Transceivers Architecture 1–13 Receiver Channel Datapath In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at the receiver input buffer as shown in Figure 1–13. The link common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage.
Page 294 1–14 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath ■ Programmable equalization—boosts the high-frequency gain of the incoming signal up to 7 dB. This compensates for the low-pass filter effects of the transmission media. The amount of high-frequency gain required depends on the loss characteristics of the physical medium.
Page 295: Clock Data Recovery
Chapter 1: Cyclone IV Transceivers Architecture 1–15 Receiver Channel Datapath Clock Data Recovery Each receiver channel has an independent CDR unit to recover the clock from the incoming serial data stream. The high-speed recovered clock is used to clock the deserializer for serial-to-parallel conversion of the received input data, and low-speed recovered clock to clock the receiver PCS blocks.
Page 296: Manual Lock Mode
The recommended transceiver reset sequence varies depending on the CDR lock mode. For more information about the reset sequence recommendations, refer to the Reset Control and Power Down for Cyclone IV GX Devices chapter. Deserializer The deserializer converts received serial data from the receiver input buffer to parallel 8- or 10-bit data.
Page 297: Word Aligner
Chapter 1: Cyclone IV Transceivers Architecture 1–17 Receiver Channel Datapath Word Aligner Figure 1–16 shows the word aligner block diagram. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization. The word...
Page 298 1–18 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath After updating the word boundary, word aligner status signals (rx_syncstatus and rx_patterndetect) are driven high for one parallel clock cycle synchronous to the most significant byte of the word alignment pattern. The rx_syncstatus and rx_patterndetect signals have the same latency as the datapath and are forwarded to the FPGA fabric to indicate the word aligner status.
Page 299 Chapter 1: Cyclone IV Transceivers Architecture 1–19 Receiver Channel Datapath Bit-Slip Mode In bit-slip mode, the rx_bitslip port controls the word aligner operation. At every rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. When the received data after bit-slipping matches the programmed word alignment pattern, the rx_patterndetect signal is driven high for one parallel clock cycle.
Page 300 1–20 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath Table 1–4 lists the synchronization state machine parameters for the word aligner in this mode. Table 1–4. Synchronization State Machine Parameters Parameter Allowed Values Number of erroneous code groups received to lose synchronization 1–64...
Page 301 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors. Receiver bit reversal—by default, the Cyclone IV GX receiver assumes LSB to MSB ■ transmission. If the link transmission order is MSB to LSB, the receiver forwards the incorrect reverse bit-ordered version of the parallel data to the FPGA fabric on the rx_dataout port.
Page 302: Deskew Fifo
1–22 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath synchronization state machine mode. In bit-slip mode, you can dynamically enable the receiver bit reversal using the rx_revbitorderwa port. When enabled, the 8-bit or 10-bit data D[7..0] or D[9..0] at the output of the word aligner is rewired to D[0..7] or D[0..9] respectively.
Page 303: Rate Match Fifo
Chapter 1: Cyclone IV Transceivers Architecture 1–23 Receiver Channel Datapath Rate Match FIFO In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. Frequency differences in the order of a few hundred ppm can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain.
Page 304: Byte Deserializer
1–24 Chapter 1: Cyclone IV Transceivers Architecture Receiver Channel Datapath Byte Deserializer The byte deserializer halves the FPGA fabric-transceiver interface frequency while doubles the parallel data width to the FPGA fabric. For example, when operating an EP4CGX150 receiver channel at 3.125 Gbps with deserialization factor of 10, the receiver PCS datapath runs at 312.5 MHz.
Page 305: Rx Phase Compensation Fifo
Chapter 1: Cyclone IV Transceivers Architecture 1–25 Receiver Channel Datapath The byte ordering block operates in either word-alignment-based byte ordering or user-controlled byte ordering modes. In word-alignment-based byte ordering mode, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data and restores the order if necessary when it detects a rising edge on the rx_syncstatus signal.
Page 306: Transceiver Clocking Architecture
The multipurpose PLLs and general-purpose PLLs located on the left side of the device generate the clocks required for the transceiver operation. The following sections describe the Cyclone IV GX transceiver clocking architecture: ■ “Input Reference Clocking” on page 1–27 “Transceiver Channel Datapath Clocking”...
Page 307: Input Reference Clocking
Chapter 1: Cyclone IV Transceivers Architecture 1–27 Transceiver Clocking Architecture Input Reference Clocking When used for transceiver, the left PLLs synthesize the input reference clock to generate the required clocks for the transceiver channels. Figure 1–25 Figure 1–26 show the sources of input reference clocks for PLLs used in the transceiver operation.
Page 308 3B and 8B respectively. These clock input pins do not have access to the clock control blocks and GCLK networks. For more details, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter. (3) Using any clock input pins other than the designated REFCLK pins as shown here to drive the MPLLs and GPLLs may have reduced jitter performance.
Page 309: Transceiver Channel Datapath Clocking
Chapter 1: Cyclone IV Transceivers Architecture 1–29 Transceiver Clocking Architecture Figure 1–27 shows an example of the termination scheme for AC-coupled connections for REFCLK pins. Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock LVDS, LVPECL, PCML (1.2 V, 1.5 V, 3.3 V)
Page 310 1–30 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture The CDR unit in each receiver channel gets the CDR clocks from one of the two multipurpose PLLs directly adjacent to the transceiver block. The CDR clocks distribution network is segmented by bidirectional tri-state buffers as shown in Figure 1–29...
Page 311: Non-Bonded Channel Configuration
PLLs directly adjacent to transceiver block where the channel resides. The Cyclone IV GX transceivers support non-bonded (×1) and bonded (×2 and ×4) channel configurations. The two configurations differ in regards to clocking and phase compensation FIFO control. Bonded configuration provides a relatively lower channel-to-channel skew between the bonded channels than in non-bonded configuration.
Page 312 1–32 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Table 1–9 lists the high- and low-speed clock sources for each channel. Table 1–9. High- and Low-Speed Clock Sources for Each Channel in Non-Bonded Channel Configuration High- and Low-Speed Clocks Sources...
Page 313 Chapter 1: Cyclone IV Transceivers Architecture 1–33 Transceiver Clocking Architecture Figure 1–31 Figure 1–32 show the high- and low-speed clock distribution for transceivers in F324 and smaller packages, and in F484 and larger packages in non-bonded channel configuration. Figure 1–31. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F324...
Page 314 1–34 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484 and Larger Packages GPLL_2 MPLL_8 TX PMA TX PMA Transceiver Block TX PMA GXBL1 TX PMA MPLL_7 Not applicable in...
Page 315 Chapter 1: Cyclone IV Transceivers Architecture 1–35 Transceiver Clocking Architecture When the byte serializer is enabled, the low-speed clock frequency is halved before feeding into the read clock of TX phase compensation FIFO. The low-speed clock is available in the FPGA fabric as tx_clkout port, which can be used in the FPGA fabric to send transmitter data and control signals.
Page 316 1–36 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Figure 1–35 shows the datapath clocking in the transmitter and receiver operation mode with the rate match FIFO. The receiver datapath clocking in configuration without the rate match FIFO is identical to Figure 1–34.
Page 317: Bonded Channel Configuration
Chapter 1: Cyclone IV Transceivers Architecture 1–37 Transceiver Clocking Architecture Bonded Channel Configuration In bonded channel configuration, the low-speed clock for the bonded channels share a common bonded clock path that reduces clock skew between the bonded channels. The phase compensation FIFOs in bonded channels share a set of pointers and control logic that results in equal FIFO latency between the bonded channels.
Page 318 1–38 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Figure 1–36 Figure 1–37 show the independent high-speed clock and bonded low-speed clock distributions for transceivers in F324 and smaller packages, and in F484 and larger packages in bonded (×2 and ×4) channel configuration.
Page 319 Chapter 1: Cyclone IV Transceivers Architecture 1–39 Transceiver Clocking Architecture Figure 1–37. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in F484 and Larger Packages 2 Bonded Channel Configuration 4 Bonded Channel Configuration GPLL_2 MPLL_8 MPLL_8 TX PMA...
Page 320 1–40 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture When the byte serializer is enabled, the common bonded low-speed clock frequency is halved before feeding to the read clock of TX phase compensation FIFO. The common bonded low-speed clock is available in FPGA fabric as coreclkout port, which can be used in FPGA fabric to send transmitter data and control signals to the bonded channels.
Page 321 Chapter 1: Cyclone IV Transceivers Architecture 1–41 Transceiver Clocking Architecture For Transmitter and Receiver operation in bonded channel configuration, the receiver PCS supports configuration with rate match FIFO, and configuration without rate match FIFO. Figure 1–39 shows the datapath clocking in Transmitter and Receiver operation with rate match FIFO in ×2 and ×4 bonded channel configurations.
Page 322 1–42 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Figure 1–39. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Bonded Channel Configuration Transmitter Channel PCS 3 Transmitter Channel PMA 3 FPGA Fabric Tx Phase Comp Byte Serializer...
Page 323: Fpga Fabric-Transceiver Interface Clocking
FPGA fabric. These clock resources use the global clock networks (GCLK) in the FPGA core. For information about the GCLK resources in the Cyclone IV GX devices, refer to Clock Networks and PLLs in Cyclone IV Devices chapter.
Page 324 1–44 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Clocking Architecture Table 1–11. FPGA Fabric-Transceiver Interface Clocks (Part 2 of 2) Clock Name Clock Description Interface Direction cal_blk_clk Transceiver calibration block clock FPGA fabric to transceiver Notes to Table 1–11: (1) Offset cancellation process that is executed after power cycle requires reconfig_clk clock. The reconfig_clk must be driven with a free-running clock and not derived from the transceiver blocks.
Page 325: Calibration Block
Chapter 1: Cyclone IV Transceivers Architecture 1–45 Calibration Block Table 1–13. Automatic RX Phase Compensation FIFO Read Clock Selection (Part 2 of 2) Channel Configuration Quartus II Selection coreclkout clock feeds the FIFO read clock for the bonded channels. With rate match FIFO coreclkout clock is the common bonded low-speed clock, which also feeds the FIFO read clock and transmitter PCS in the bonded channels.
Page 326: Pci-Express Hard Ip Block
1–46 Chapter 1: Cyclone IV Transceivers Architecture PCI-Express Hard IP Block The calibration block internally generates a constant internal reference voltage, independent of PVT variations and uses this voltage and the external reference resistor on the RREF pin to generate constant reference currents. The OCT calibration circuit calibrates the OCT resistors present in the transceiver channels.
Page 327: Transceiver Functional Modes
1–43: (1) Applicable for PCIe ×1, ×2, and ×4 implementations with hard IP blocks only. Transceiver Functional Modes The Cyclone IV GX transceiver supports the functional modes as listed in Table 1–14 for protocol implementation. Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 1 of 2)
Page 328: Basic Mode
High-speed SERDES, CDR page 1–76 Basic Mode The Cyclone IV GX transceiver channel datapath is highly flexible in Basic mode to implement proprietary protocols. SATA, V-by-One, and Display Port protocol implementations in Cyclone IV GX transceiver are supported with Basic mode.
Page 329 Chapter 1: Cyclone IV Transceivers Architecture 1–49 Transceiver Functional Modes Figure 1–45 Figure 1–46 show the supported transceiver configurations in Basic mode with the 8-bit and 10-bit PMA-PCS interface width respectively. Figure 1–45. Supported Transceiver Configurations in Basic Mode with the 8-bit PMA-PCS...
Page 330: Rate Match Fifo Operation In Basic Mode
1–50 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–46. Transceiver Configurations in Basic Mode with a 10-Bit Wide PMA-to-PCS Interface Functional Mode Basic (10-Bit PMA-PCS Interface Width) Channel Bonding ×1, ×2, ×4 Low-Latency PCS Disabled Enabled Word Aligner...
Page 331 Chapter 1: Cyclone IV Transceivers Architecture 1–51 Transceiver Functional Modes ■ transmitter in electrical idle ■ receiver signal detect receiver spread spectrum clocking ■ Low-Latency PCS Operation When configured in low-latency PCS operation, the following blocks in the transceiver PCS are bypassed, resulting in a lower latency PCS datapath: ■...
Page 332: Pci Express (Pipe) Mode
Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Receiver Spread Spectrum Clocking Asynchronous SSC is not supported in Cyclone IV devices. You can implement only synchronous SSC for SATA, V-by-One, and Display Port protocols in Basic mode. PCI Express (PIPE) Mode PIPE mode provides the transceiver channel datapath configuration that supports ×1,...
Page 333 Chapter 1: Cyclone IV Transceivers Architecture 1–53 Transceiver Functional Modes Configuring the hard IP module requires using the PCI Express Compiler. When configuring the transceiver for PCIe implementation with hard IP module, the byte serializer and deserializer are not enabled, providing an 8-bit transceiver-PIPE-hard IP data interface width running at 250 MHz clock frequency.
Page 334: Pipe Interface
(1) When used with PCIe hard IP block, the byte SERDES is not used. In this case, the data ports are 8 bits wide and control identifier is 1 bit wide. (2) Cyclone IV GX transceivers do not implement power saving measures in lower power states (P0s, P1, and P2), except when putting the transmitter buffer in electrical idle in the lower power states.
Page 335: Electrical Idle Control
3'b000 Electrical Idle Control The Cyclone IV GX transceivers support transmitter buffer in electrical idle state using the tx_forceelecidle port. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant to the PCIe Base Specification 2.0 for Gen1 signaling rate.
Page 336: Signal Detect At Receiver
FPGA fabric on the pipestatus[2..0] port from each channel. Low-Latency Synchronous PCIe In PIPE mode, the Cyclone IV GX transceiver supports a lower latency in synchronous PCIe by reducing the latency across the rate match FIFO. In synchronous PCIe, the system uses a common reference clocking that gives a 0 ppm difference between the upstream transmitter's and local receiver's reference clock.
Page 337: Fast Recovery From P0S State
L0s to L0 (PIPE P0s to P0) power states. The PHY must acquire bit and byte synchronization when transitioning from L0s to L0 state between 16 ns to 4 µs. Each Cyclone IV GX receiver channel has built-in fast recovery circuit that allows the receiver to meet the requirement when enabled.
Page 338: Reset Requirement
B5BC 4ABC tx_ctrldetect[1..0] tx_forcedispcompliance Reset Requirement Cyclone IV GX devices meets the PCIe reset time requirement from device power up to the link active state with the configuration schemes listed in Table 1–17. Table 1–18. Electrical Idle Inference Conditions Device...
Page 339 Chapter 1: Cyclone IV Transceivers Architecture 1–59 Transceiver Functional Modes Cyclone IV GX transceivers do not have built-in support for some PCS functions such as auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in a user logic or external circuits.
Page 340 1–60 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–55 shows the transceiver channel datapath and clocking when configured in GIGE mode. Figure 1–55. Transceiver Channel Datapath and Clocking when Configured in GIGE Mode Transmitter Channel PCS Transmitter Channel PMA...
Page 341 Chapter 1: Cyclone IV Transceivers Architecture 1–61 Transceiver Functional Modes Figure 1–56 shows the transceiver configuration in GIGE mode. Figure 1–56. Transceiver Configuration in GIGE Mode Functional Mode GIGE Channel Bonding ×1 Low-Latency PCS Disabled Word Aligner (Pattern Length) Automatic Synchronization...
Page 342: Running Disparity Preservation With Idle Ordered Set
1–62 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–57 shows an example of even numbers of /Dx.y/ between the last automatically sent /K28.5/ and the first user-sent /K28.5/. The first user-sent /K28.5/ code group received at an odd code group boundary in cycle n + 3 takes the receiver synchronization state machine in Loss-of-Sync state.
Page 343: Clock Frequency Compensation
Chapter 1: Cyclone IV Transceivers Architecture 1–63 Transceiver Functional Modes Clock Frequency Compensation In GIGE mode, the rate match FIFO compensates up to ±100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. The GIGE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering to the...
Page 344: Serial Rapidio Mode
■ lane synchronization state machine Cyclone IV GX transceivers do not have built-in support for some PCS functions such as pseudo-random idle sequence generation and lane alignment in ×4 bonded channel configuration. If required, you must implement these functions in a user logics or external circuits.
Page 345 Chapter 1: Cyclone IV Transceivers Architecture 1–65 Transceiver Functional Modes Figure 1–60 shows the transceiver channel datapath and clocking when configured in Serial RapidIO mode. Figure 1–60. Transceiver Channel Datapath and Clocking when Configured in Serial RapidIO Mode Transmitter Channel PCS...
Page 346: Lane Synchronization
1–66 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–61 shows the transceiver configuration in Serial RapidIO mode. Figure 1–61. Transceiver Configuration in Serial RapidIO Mode Functional Mode SRIO Channel Bonding ×1 Low-Latency PCS Disabled Word Aligner (Pattern Length)
Page 347: Clock Frequency Compensation
200 ppm. XAUI Mode XAUI mode provides the bonded (×4) transceiver channel datapath configuration for XAUI protocol implementation. The Cyclone IV GX transceivers configured in XAUI mode provides the following functions: ■ XGMII-to-PCS code conversion at transmitter datapath PCS-to-XGMII code conversion at receiver datapath ■...
Page 348 1–68 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes converted within the XGMII extender sublayer into an 8B/10B encoded data stream. Each data stream is then transmitted across a single differential pair running at 3.125 Gbps. At the XAUI receiver, the incoming data is decoded and mapped back to the 32- bit XGMII format.
Page 349 Chapter 1: Cyclone IV Transceivers Architecture 1–69 Transceiver Functional Modes Figure 1–63 shows the transceiver channel datapath and clocking when configured in XAUI mode. Figure 1–63. Transceiver Channel Datapath and Clocking when Configured in XAUI Mode Transmitter Channel PCS 3...
Page 350: Xgmii And Pcs Code Conversions
1–70 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–64 shows the transceiver configuration in XAUI mode. Figure 1–64. Transceiver Configuration in XAUI Mode Functional Mode XAUI Channel Bonding ×4 Low-Latency PCS Disabled Word Aligner (Pattern Length) Automatic Synchronization...
Page 351: Channel Deskewing
Chapter 1: Cyclone IV Transceivers Architecture 1–71 Transceiver Functional Modes Table 1–21. XGMII Character to PCS Code Groups Mapping (Part 2 of 2) (2), XGMII TXC XGMII TXD PCS Code Group Description Any other value K30.7 Invalid XGMII character Notes to Table 1–21:...
Page 352: Lane Synchronization
1–72 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes ■ Channel alignment is acquired if three additional aligned ||A|| columns are observed at the output of the deskew FIFOs of the four channels after alignment of the first ||A|| column.
Page 353: Clock Rate Compensation
This mode supports non-bonded (×1) and bonded (×4) channel configurations, and is typically used to support CPRI and OBSAI protocols that require accurate delay measurements along the datapath. The Cyclone IV GX transceivers configured in Deterministic Latency mode provides the following features: ■...
Page 354 1–74 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Functional Modes Figure 1–66 shows the transceiver channel datapath and clocking when configured in deterministic latency mode. Figure 1–66. Transceiver Channel Datapath and Clocking when Configured in Deterministic Latency Mode Transmitter Channel PCS...
Page 355: Registered Mode Phase Compensation Fifo
The protocols require the accuracy of round trip delay measurement for single-hop and multi-hop connections to be within ± 16.276 ns. The Cyclone IV GX transceivers support the following CPRI and OBSAI line rates using Deterministic Latency mode: CPRI —614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, and 3.072 Gbps...
Page 356: Receive Bit-Slip Indication
SDI mode provides the non-bonded (×1) transceiver channel datapath configuration for HD- and 3G-SDI protocol implementations. Cyclone IV GX transceivers configured in SDI mode provides the serialization and deserialization functions that supports the SDI data rates as listed in Table 1–24.
Page 357 Chapter 1: Cyclone IV Transceivers Architecture 1–77 Transceiver Functional Modes Figure 1–68 shows the transceiver channel datapath and clocking when configured in SDI mode. Figure 1–68. Transceiver Channel Datapath and Clocking when Configured in SDI Mode Transmitter Channel PCS Transmitter Channel PMA...
Page 358: Loopback
Loopback Cyclone IV GX devices provide three loopback options that allow you to verify the operation of different functional blocks in the transceiver channel. The following loopback modes are available: reverse parallel loopback (available only for PIPE mode) ■...
Page 359: Reverse Parallel Loopback
Chapter 1: Cyclone IV Transceivers Architecture 1–79 Loopback Reverse Parallel Loopback The reverse parallel loopback option is only available for PIPE mode. In this mode, the received serial data passes through the receiver CDR, deserializer, word aligner, and rate match FIFO before looping back to the transmitter serializer and transmitted...
Page 360: Reverse Serial Loopback
1–80 Chapter 1: Cyclone IV Transceivers Architecture Loopback Serial loopback mode can only be dynamically enabled or disabled during user mode by performing a dynamic channel reconfiguration. Figure 1–71. Serial Loopback Path FPGA Transceiver Fabric Tx PMA Serializer Tx PCS...
Page 361: Self Test Modes
(3) Pre-CDR reverse serial loopback path. Self Test Modes Each transceiver channel in the Cyclone IV GX device contains modules for pattern generator and verifier. Using these built-in features, you can verify the functionality of the functional blocks in the transceiver channel without requiring user logic. The self test functionality is provided as an optional mechanism for debugging transceiver channels.
Page 362: Bist
1–82 Chapter 1: Cyclone IV Transceivers Architecture Self Test Modes BIST Figure 1–73 shows the datapath for BIST incremental data pattern test mode. The BIST incremental data generator and verifier are located near the FPGA fabric in the PCS block of the transceiver channel.
Page 363: Prbs
Chapter 1: Cyclone IV Transceivers Architecture 1–83 Self Test Modes PRBS Figure 1–74 shows the datapath for the PRBS, high and low frequency pattern test modes. The pattern generator is located in TX PCS before the serializer, and PRBS pattern verifier located in RX PCS after the word aligner.
Page 364 1–84 Chapter 1: Cyclone IV Transceivers Architecture Self Test Modes Table 1–25. PRBS, High and Low Frequency Patterns, and Channel Settings (Part 2 of 2) 8-bit Channel Width 10-bit Channel Width Maximum Maximum Maximum Maximum Channel Channel Data Rate Data Rate...
Page 365: Transceiver Top-Level Port Lists
Chapter 1: Cyclone IV Transceivers Architecture 1–85 Transceiver Top-Level Port Lists Transceiver Top-Level Port Lists Table 1–26 through Table 1–29 provide descriptions of the ports available when instantiating a transceiver using the ALTGX megafunction. The ALTGX megafunction requires a relatively small number of signals. There are also a large number of optional signals that facilitate debugging by providing information about the state of the transceiver.
Page 366 1–86 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Top-Level Port Lists Table 1–26. Transmitter Ports in ALTGX Megafunction for Cyclone IV GX Input/ Block Port Name Clock Domain Description Output Synchronous to Parallel data input from the FPGA fabric to the transmitter.
Page 367 Chapter 1: Cyclone IV Transceivers Architecture 1–87 Transceiver Top-Level Port Lists Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 1 of 3) Input/ Block Port Name Clock Domain Description Output Synchronous to tx_clkout (non- bonded modes with rate match Word alignment synchronization status indicator.
Page 368 1–88 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Top-Level Port Lists Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 2 of 3) Input/ Block Port Name Clock Domain Description Output Rate match FIFO full status indicator.
Page 369 Chapter 1: Cyclone IV Transceivers Architecture 1–89 Transceiver Top-Level Port Lists Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 3 of 3) Input/ Block Port Name Clock Domain Description Output Optional read clock port for the RX phase compensation...
Page 370 1–90 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Top-Level Port Lists Table 1–28. PIPE Interface Ports in ALTGX Megafunction for Cyclone IV GX (Part 1 of 2) Input/ Port Name Clock Domain Description Output 125-MHz clock for receiver detect and offset cancellation only in PIPE...
Page 371 Chapter 1: Cyclone IV Transceivers Architecture 1–91 Transceiver Top-Level Port Lists Table 1–28. PIPE Interface Ports in ALTGX Megafunction for Cyclone IV GX (Part 2 of 2) Input/ Port Name Clock Domain Description Output PIPE receiver status port. Signal is 3 bits wide and is encoded as follows: ■...
Page 372 1–92 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Top-Level Port Lists Table 1–29. Multipurpose PLL, General Purpose PLL and Miscellaneous Ports in ALTGX Megafunction for Cyclone IV GX (Part 2 of 2) Input/ Block Port Name Clock Domain Description Output Transceiver block power down.
Page 373: Document Revision History
Updated information for the Quartus II software version 10.0 release. ■ Reset control, power down, and dynamic reconfiguration information moved to ■ July 2010 new Cyclone IV Reset Control and Power Down and Cyclone IV Dynamic Reconfiguration chapters. February 2015 Altera Corporation Cyclone IV Device Handbook, Volume 2...
Page 374 1–94 Chapter 1: Cyclone IV Transceivers Architecture Document Revision History Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2...
Page 375 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 376: Chapter 2. Cyclone Iv Reset Control And Power Down
User Reset and Power-Down Signals User Reset and Power-Down Signals Each transceiver channel in the Cyclone IV GX device has individual reset signals to reset its physical coding sublayer (PCS) and physical medium attachment (PMA). The transceiver block also has a power-down signal that affects the multipurpose phase-locked loops (PLLs), general purpose PLLs, and all the channels in the transceiver block.
Page 377: Blocks Affected By The Reset And Power-Down Signals
Chapter 2: Cyclone IV Reset Control and Power Down 2–3 User Reset and Power-Down Signals Table 2–2 lists the power-down signals available for each transceiver block. Table 2–2. Transceiver Block Power-Down Signals Signal Description Resets the transceiver PLL. The pll_areset signal is asserted in two conditions: During reset sequence, the signal is asserted to reset the transceiver PLL.
Page 378: Transceiver Reset Sequences
) functional mode, transceiver channels can be either bonded or non-bonded and need to follow a specific reset sequence. The two categories of reset sequences for Cyclone IV GX devices described in this chapter are: ■ “All Supported Functional Modes Except the PCIe Functional Mode” on page 2–6—describes the reset sequences in bonded and non-bonded...
Page 379 Figure 2–2 and the associated references listed in the notes for the figure. Altera strongly recommends adhering to these reset sequences for proper operation of the Cyclone IV GX transceiver. Figure 2–2 shows the transceiver reset sequences for Cyclone IV GX devices.
Page 380: All Supported Functional Modes Except The Pcie Functional Mode
(lock-to-data), depending on the logic levels on the rx_locktorefclk and rx_locktodata signals. With the receiver CDR in manual lock mode, you can either configure the transceiver channels in the Cyclone IV GX device in a non-bonded configuration or a bonded configuration. In a bonded configuration, for example in XAUI mode, four channels are bonded together.
Page 381 Chapter 2: Cyclone IV Reset Control and Power Down 2–7 Transceiver Reset Sequences Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager in Basic ×4 functional...
Page 382 2–8 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. When the receiver CDR is in automatic lock mode, use the reset sequence shown in Figure 2–4.
Page 383 Chapter 2: Cyclone IV Reset Control and Power Down 2–9 Transceiver Reset Sequences 4. For the receiver operation, after deassertion of busy signal, wait for two parallel clock cycles to deassert the rx_analogreset signal. 5. Wait for the rx_freqlocked signal from each channel to go high. The rx_freqlocked signal of each channel may go high at different times (indicated by the slashed pattern at marker 7).
Page 384: Non-Bonded Channel Configuration
2–10 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences As shown in Figure 2–5, perform the following reset procedure for the receiver CDR in manual lock mode configuration: 1. After power up, assert pll_areset for a minimum period of 1 s (the time between markers 1 and 2).
Page 385 Chapter 2: Cyclone IV Reset Control and Power Down 2–11 Transceiver Reset Sequences Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager, use the same reset sequence shown in Figure 2–3 on page...
Page 386 2–12 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences Receiver Only Channel—Receiver CDR in Manual Lock Mode This configuration contains only a receiver channel. If you create a Receiver Only instance in the ALTGX MegaWizard Plug-In Manager with receiver CDR in manual...
Page 387 Chapter 2: Cyclone IV Reset Control and Power Down 2–13 Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and a receiver channel. If you create a Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with...
Page 388 2–14 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. If you create a Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with...
Page 389: Reset Sequence In Loss Of Link Conditions
Chapter 2: Cyclone IV Reset Control and Power Down 2–15 Transceiver Reset Sequences 4. Wait for at least t (the time between markers 6 and 7), then deassert LTR_LTD_Manual the rx_locktorefclk signal. At the same time, assert the rx_locktodata signal (marker 7).
Page 390 2–16 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences This solution may violate some of the protocol specific requirements. In such case, you can use Manual CDR lock option. For Manual CDR lock mode, rx_freqlocked signal is not available. Upon ■...
Page 391: Pcie Functional Mode
PCIe Functional Mode You can configure PCIe functional mode with or without the receiver clock rate compensation FIFO in the Cyclone IV GX device. The reset sequence remains the same whether or not you use the receiver clock rate compensation FIFO.
Page 392: Pcie Initialization/Compliance Phase
2–18 Chapter 2: Cyclone IV Reset Control and Power Down Transceiver Reset Sequences PCIe Initialization/Compliance Phase After the device is powered up, a PCIe-compliant device goes through the compliance phase during initialization. The rx_digitalreset signal must be deasserted during this compliance phase to achieve transitions on the pipephydonestatus signal, as expected by the link layer.
Page 393: Dynamic Reconfiguration Reset Sequences
Notes to Figure 2–11: (1) The pll_configupdate and pll_areset signals are driven by the ALTPLL_RECONFIG megafunction. For more information, refer to AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices and the Cyclone IV Dynamic Reconfiguration chapter. (2) For t...
Page 394: Reset Sequence In Channel Reconfiguration Mode
2–20 Chapter 2: Cyclone IV Reset Control and Power Down Dynamic Reconfiguration Reset Sequences 2. After the PLL is reset, wait for the pll_locked signal to go high (marker 4) indicating that the PLL is locked to the input reference clock. After the assertion of the pll_locked signal, deassert the tx_digitalreset signal (marker 5).
Page 395: Power Down
Power Down The Quartus II software automatically selects the power-down channel feature, which takes effect when you configure the Cyclone IV GX device. All unused transceiver channels and blocks are powered down to reduce overall power consumption. The gxb_powerdown signal is an optional transceiver block signal. It powers down all transceiver channels and all functional blocks in the transceiver block.
Page 396: Simulation Requirements
2–22 Chapter 2: Cyclone IV Reset Control and Power Down Simulation Requirements The deassertion of the busy signal indicates proper completion of the offset cancellation process on the receiver channel. Figure 2–13. Sample Reset Sequence of a Receiver and Transmitter Channels-Receiver CDR in Automatic Lock Mode with the Optional gxb_powerdown Signal 1 µs...
Page 397: Reference Information
Chapter 2: Cyclone IV Reset Control and Power Down 2–23 Reference Information ■ In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least one parallel clock cycle before transmitting normal data for correct simulation behavior. Reference Information...
Page 398: Document Revision History
2–24 Chapter 2: Cyclone IV Reset Control and Power Down Document Revision History Document Revision History Table 2–8 lists the revision history for this chapter. Table 2–8. Document Revision History Date Version Changes Removed the rx_pll_locked signal from the “Sample Reset Sequence of ■...
Page 399: Chapter 3. Cyclone Iv Dynamic Reconfiguration
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 400: Dynamic Reconfiguration Controller Architecture
The dynamic reconfiguration controller is a soft intellectual property (IP) that utilizes FPGA-fabric resources. You can use only one controller per transceiver block. You cannot use the dynamic reconfiguration controller to control multiple Cyclone IV devices or any off-chip interfaces.
Page 401 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–3 Dynamic Reconfiguration Controller Architecture Figure 3–1 shows a conceptual view of the dynamic reconfiguration controller architecture. For a detailed description of the inputs and outputs of the ALTGX_RECONFIG instance, refer to “Error Indication During Dynamic Reconfiguration”...
Page 402: Dynamic Reconfiguration Controller Port List
3–4 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Controller Port List Dynamic Reconfiguration Controller Port List Table 3–2 lists the input control ports and output status ports of the dynamic reconfiguration controller. Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 1 of 7)
Page 403 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–5 Dynamic Reconfiguration Controller Port List Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 2 of 7) Input/ Port Name Description Output FPGA Fabric and ALTGX_RECONFIG Interface Signals Assert this signal for one reconfig_clk clock cycle to initiate a write transaction from the ALTGX_RECONFIG instance to the ALTGX instance.
Page 404 3–6 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Controller Port List Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 3 of 7) Input/ Port Name Description Output Enabled by the ALTGX_RECONFIG MegaWizard Plug-In Manager when you enable the Use 'logical_channel_address' port for Analog controls reconfiguration option in the Analog controls screen.
Page 405 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–7 Dynamic Reconfiguration Controller Port List Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 4 of 7) Input/ Port Name Description Output Analog Settings Control/Status Signals This is an optional transmit buffer V control signal.
Page 406 3–8 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Controller Port List Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 5 of 7) Input/ Port Name Description Output This is an optional pre-emphasis write control for the transmit buffer. Depending on what value you set at this input, the controller dynamically writes the value to the pre-emphasis control register of the transmit buffer.
Page 407 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–9 Dynamic Reconfiguration Controller Port List Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 6 of 7) Input/ Port Name Description Output This is an optional equalizer DC gain write control. The width of this signal is fixed to 2 bits if you enable either the Use 'logical_channel_address' port for Analog controls reconfiguration option or the Use same control signal for all the channels option in the Analog controls screen.
Page 408: Offset Cancellation Feature
Offset Cancellation Feature The Cyclone IV GX devices provide an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature (PVT). These variations create an offset in the analog circuit voltages, pushing them out of the expected range.
Page 409 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–11 Dynamic Reconfiguration Controller Port List The Offset cancellation for Receiver channels option is automatically enabled in both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers for Receiver and Transmitter and Receiver only configurations. It is not available for Transmitter only configurations.
Page 410: Functional Simulation Of The Offset Cancellation Process
Channel reconfiguration PLL reconfiguration ■ Table 3–3 lists the supported dynamic reconfiguration modes for Cyclone IV GX devices. Table 3–3. Cyclone IV GX Supported Dynamic Reconfiguration Mode (Part 1 of 2) Operational Mode Quartus II Instances Transmitter Dynamic Reconfiguration .mif...
Page 411: Pma Controls Reconfiguration Mode
Chapter 3: Cyclone IV Dynamic Reconfiguration 3–13 Dynamic Reconfiguration Modes Table 3–3. Cyclone IV GX Supported Dynamic Reconfiguration Mode (Part 2 of 2) Operational Mode Quartus II Instances Transmitter Dynamic Reconfiguration .mif Transmitter Receiver ALTGX_ ALTPLL_ Supported Mode Requirements ALTGX...
Page 412: Method 1: Using Logical_Channel_Address To Reconfigure Specific Transceiver Channels
3–14 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes There are three methods that you can use to dynamically reconfigure the PMA controls of a transceiver channel: “Method 1: Using logical_channel_address to Reconfigure Specific Transceiver ■ Channels” on page 3–14 “Method 2: Writing the Same Control Signals to Control All the Transceiver...
Page 413 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–15 Dynamic Reconfiguration Modes Figure 3–4 shows the write transaction waveform for Method 1. Figure 3–4. Write Transaction Waveform—Use ‘logical_channel_address port’ Option reconfig_clk write_all 2'b00 2'b10 rx_tx_duplex_sel [1:0] 2'b00 2'b01 logical_channel_address [1:0] busy 3'b111...
Page 414: Method 2: Writing The Same Control Signals To Control All The Transceiver Channels
3–16 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes Figure 3–5 shows the read transaction waveform for Method 1. Figure 3–5. Read Transaction Waveform—Use ‘logical_channel_address port’ Option reconfig_clk read 2'b00 2'b10 rx_tx_duplex_sel [1:0] 2'b00 2'b01 logical_channel_address [1:0] busy data_valid...
Page 415 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–17 Dynamic Reconfiguration Modes PMA Control Ports Used in a Read Transaction ■ tx_vodctrl_out is 3 bits per channel ■ tx_preemp_out is 5 bits per channel rx_eqdcgain_out is 2 bits per channel ■ ■...
Page 416 3–18 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes Read Transaction If you want to read the existing values from a specific channel connected to the ALTGX_RECONFIG instance, observe the corresponding byte positions of the PMA control output port after the read transaction is completed.
Page 417 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–19 Dynamic Reconfiguration Modes Method 3: Writing Different Control Signals for all the Transceiver Channels at the Same Time If you disable the Use the same control signal for all the channels option, the PMA control ports for a write transaction are separate for each channel.
Page 418 3–18. This is the slowest method. You have to write all the PMA settings for all channels even if you may only be changing one parameter on the channel. Altera recommends using the logical_channel_address method for time-critical applications. For each method, you can additionally reconfigure the PMA setting of both transmitter and receiver portion, transmitter portion only, or receiver portion only of the transceiver channel.
Page 419: Transceiver Channel Reconfiguration Mode
Chapter 3: Cyclone IV Dynamic Reconfiguration 3–21 Dynamic Reconfiguration Modes Figure 3–9 shows the connection for PMA reconfiguration mode. Figure 3–9. ALTGX and ALTGX_RECONFIG Connection for PMA Reconfiguration Mode ALTGX_RECONFIG ALTGX reconfig_fromgxb[n..0] reconfig_clk reconfig_togxb[3..0] TX PMA TX PCS data_valid read...
Page 420: Channel Interface Reconfiguration Mode
3–22 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes The following are the channel reconfiguration mode options: ■ Channel interface reconfiguration Data rate division at receiver channel ■ Channel Interface Reconfiguration Mode Enable this option if the reconfiguration of the transceiver channel involves the following changes: ■...
Page 421 FPGA fabric-transceiver channel interface signals. Table 3–4. tx_datainfull[21..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions FPGA Fabric-Transceiver Channel Transmit Signal Description (Based on Cyclone IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) tx_datainfull[7:0]: 8-bit data (tx_datain)
Page 422 Table 3–5. rx_dataoutfull[31..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 3) FPGA Fabric-Transceiver Channel Receive Signal Description (Based on Cyclone IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) The following signals are used in 8-bit 8B/10B modes:...
Page 423 Dynamic Reconfiguration Modes Table 3–5. rx_dataoutfull[31..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 2 of 3) FPGA Fabric-Transceiver Channel Receive Signal Description (Based on Cyclone IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) Two 8-bit unencoded Data (rx_dataout)
Page 424: Data Rate Reconfiguration Mode Using Rx Local Divider
Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes Table 3–5. rx_dataoutfull[31..0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 3 of 3) FPGA Fabric-Transceiver Channel Receive Signal Description (Based on Cyclone IV GX Supported FPGA Interface Description Fabric-Transceiver Channel Interface Widths) Two 10-bit Data (rx_dataout)
Page 425: Control And Status Signals For Channel Reconfiguration
Chapter 3: Cyclone IV Dynamic Reconfiguration 3–27 Dynamic Reconfiguration Modes Control and Status Signals for Channel Reconfiguration The various control and status signals involved in the Channel Reconfiguration mode are as follows. Refer to “Dynamic Reconfiguration Controller Port List” on page 3–4 for the descriptions of the control and status signals.
Page 426 Dynamic Reconfiguration Modes Clocking/Interface Options The following describes the Clocking/Interface options available in Cyclone IV GX devices. The core clocking setup describes the transceiver core clocks that are the write and read clocks of the Transmit Phase Compensation FIFO and the Receive Phase Compensation FIFO, respectively.
Page 427 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–29 Dynamic Reconfiguration Modes Option 1: Share a Single Transmitter Core Clock Between Transmitters ■ Enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the write clock to the Transmitter Phase Compensation FIFOs of the remaining channels in the transceiver block.
Page 428 3–30 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes Option 2: Use the Respective Channel Transmitter Core Clocks ■ Enable this option if you want the individual transmitter channel tx_clkout signals to provide the write clock to their respective Transmit Phase Compensation FIFOs.
Page 429 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–31 Dynamic Reconfiguration Modes Option 1: Share a Single Transmitter Core Clock Between Receivers ■ Enable this option if you want tx_clkout of the first channel (channel 0) of the transceiver block to provide the read clock to the Receive Phase Compensation FIFOs of the remaining receiver channels in the transceiver block.
Page 430 3–32 Chapter 3: Cyclone IV Dynamic Reconfiguration Dynamic Reconfiguration Modes Option 2: Use the Respective Channel Transmitter Core Clocks ■ Enable this option if you want the individual transmitter channel’s tx_clkout signal to provide the read clock to its respective Receive Phase Compensation FIFO.
Page 431: Pll Reconfiguration Mode
High-speed serial clock generated by the MPLL PLL Reconfiguration Mode Cyclone IV GX device support the PLL reconfiguration support through the ALTPLL_RECONFIG MegaWizard. You can use this mode to reconfigure the multipurpose PLL or general purpose PLL used to clock the transceiver channel without affecting the remaining blocks of the channel.
Page 432 (3) You need two ALTPLL_RECONFIG controllers if you have two separate ALTGX instances with transceiver PLL instantiated in each ALTGX instance. For more information about connecting the ALTPLL_RECONFIG and ALTGX instances, refer to the AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices. Cyclone IV Device Handbook,...
Page 433 Chapter 3: Cyclone IV Dynamic Reconfiguration 3–35 Dynamic Reconfiguration Modes Table 3–7 lists the ALTGX megafunction ports for PLL Reconfiguration mode. Table 3–7. ALTGX Megafunction Port List for PLL Reconfiguration Mode Input/ Port Name Description Comments Output Resets the transceiver PLL. The...
Page 434: Error Indication During Dynamic Reconfiguration
3–36 Chapter 3: Cyclone IV Dynamic Reconfiguration Error Indication During Dynamic Reconfiguration If you are reconfiguring the multipurpose PLL with a different M counter value, follow these steps: 1. During transceiver PLL reconfiguration, assert tx_digitalreset, rx_digitalreset, and rx_analogreset signals. 2. Perform PLL reconfiguration to update the multipurpose PLL with the PLL .mif files.
Page 435: Functional Simulation Of The Dynamic Reconfiguration Process
Chapter 3: Cyclone IV Dynamic Reconfiguration 3–37 Functional Simulation of the Dynamic Reconfiguration Process Functional Simulation of the Dynamic Reconfiguration Process This section describes the points to be considered during functional simulation of the dynamic reconfiguration process. ■ You must connect the ALTGX_RECONFIG instance to the ALTGX_instance/ALTGX instances in your design for functional simulation.
Page 436 3–38 Chapter 3: Cyclone IV Dynamic Reconfiguration Document Revision History Cyclone IV Device Handbook, November 2011 Altera Corporation Volume 2...
Page 437 Cyclone IV Device Handbook, Volume 3 Cyclone IV Device Handbook, Volume 3 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V3-2.1...
Page 438 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 439 How to Contact Altera ........
Page 440 Contents Cyclone IV Device Handbook, December 2016 Altera Corporation Volume 3...
Page 441: Chapter Revision Dates
Chapter Revision Dates The chapters in this document, Cyclone IV Device Handbook, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Cyclone IV Device Datasheet Revised: December 2016 Part Number: CYIV-53001-2.1...
Page 442 Chapter Revision Dates Cyclone IV Device Handbook, December 2016 Altera Corporation Volume 3...
Page 443: Additional Information
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
Page 444 A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Cyclone IV Device Handbook, December 2016 Altera Corporation Volume 3...
Page 445: Section I. Device Datasheet
® This section provides the Cyclone IV device datasheet. It includes the following chapter: Chapter 1, Cyclone IV Device Datasheet ■ Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
Page 447 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Page 448 1–2 Chapter 1: Cyclone IV Device Datasheet Operating Conditions Cyclone IV E industrial devices I7 are offered with extended operating temperature range. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Cyclone IV devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms.
Page 449 = 4.60 Figure 1–1 shows the methodology to determine the overshoot duration. The overshoot voltage is shown in red and is present on the input pin of the Cyclone IV device at over 4.3 V but below 4.4 V. From Table 1–2, for an overshoot of 4.3 V, the...
Page 450 Table 1–3 Table 1–4 list the steady-state voltage and current values expected from Cyclone IV E and Cyclone IV GX devices. All supplies must be strictly monotonic without plateaus. (1), Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices...
Page 451 Notes to Table 1–3: (1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. (2) V for all I/O banks must be powered up during device operation.
Page 452 1–6 Chapter 1: Cyclone IV Device Datasheet Operating Conditions Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2) Symbol Parameter Conditions Unit Transceiver PMA and auxiliary power — 2.375 2.625 CCA_GXB supply Transceiver PMA and auxiliary power —...
Page 453 Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 1–7 lists bus hold specifications for Cyclone IV devices. Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 1 of 2) CCIO Parameter Condition...
Page 454: Oct Specifications
1–8 Chapter 1: Cyclone IV Device Datasheet Operating Conditions Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 2 of 2) CCIO Parameter Condition Unit Bus hold trip — 0.375 1.125 0.68 1.07 point Note to Table 1–7: (1) Bus hold trip points are based on the calculated input voltages from the JEDEC standard.
Page 455 Chapter 1: Cyclone IV Device Datasheet 1–9 Operating Conditions The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up. Use Table 1–10 Equation 1–1 to determine the final OCT resistance considering the variations after calibration at device power-up.
Page 456: Pin Capacitance
MF = 0.963 × 1.157 = 1.114 = 50 × 1.114 = 55.71  final Pin Capacitance Table 1–11 lists the pin capacitance for Cyclone IV devices. Table 1–11. Pin Capacitance for Cyclone IV Devices Typical – Typical – Typical –...
Page 457: Internal Weak Pull-Up And Weak Pull-Down Resistor
Internal Weak Pull-Up and Weak Pull-Down Resistor Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV devices. Table 1–12. Internal Weak Pull - Up and Weak Pull - Down Resistor Values for Cyclone IV Devices Symbol Parameter Conditions Unit (2), = 3.3 V ±...
Page 458: Schmitt Trigger Input
Operating Conditions Schmitt Trigger Input Cyclone IV devices support Schmitt trigger input on the TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rate.
Page 459 Chapter 1: Cyclone IV Device Datasheet 1–13 Operating Conditions - Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone IV Devices Table 1–16. Single CCIO Standard SSTL – 2.375 2.625 1.19 1.25 1.31 Class I, II 0.04 0.04 SSTL - 18 –...
Page 460 For more information about receiver input and transmitter output waveforms, and for other differential I/O standards, refer to the I/O Features in Cyclone IV Devices chapter. Table 1–18. Differential SSTL I/O Standard Specifications for Cyclone IV Devices Swing(AC) CCIO Swing(DC)
Page 461 Chapter 1: Cyclone IV Device Datasheet 1–15 Operating Conditions Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices (Part 2 of 2) (mV) (mV) CCIO I/O Standard Min Max Condition  500 Mbps 0.05 1.80 LVDS 500 Mbps  D (Column 2.375...
Page 462: Power Consumption
3 of the Quartus II Handbook. Switching Characteristics This section provides performance characteristics of Cyclone IV core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary or Final. Preliminary characteristics are created using simulation results, process data, and ■...
Page 463: Transceiver Performance Specifications
Chapter 1: Cyclone IV Device Datasheet 1–17 Switching Characteristics Transceiver Performance Specifications Table 1–21 lists the Cyclone IV GX transceiver specifications. Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4) C7, I7 Symbol/ Conditions Unit Description...
Page 464 1–18 Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 2 of 4) C7, I7 Symbol/ Conditions Unit Description Receiver 1.4 V PCML, Supported I/O 1.5 V PCML, Standards 2.5 V PCML,...
Page 465 Chapter 1: Cyclone IV Device Datasheet 1–19 Switching Characteristics Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4) C7, I7 Symbol/ Conditions Unit Description Signal detect/loss PIPE mode — — — threshold (10) — — —...
Page 466 1–20 Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4) C7, I7 Symbol/ Conditions Unit Description PLD-Transceiver Interface Interface speed (F324 and smaller — — — — package)
Page 467 Chapter 1: Cyclone IV Device Datasheet 1–21 Switching Characteristics Figure 1–2 shows the lock time parameters in manual mode. LTD = lock-to-data. LTR = lock-to-reference. Figure 1–2. Lock Time Parameters for Manual Mode Reset Signals rx _ analogreset rx _ digitalreset...
Page 468 1–22 Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Figure 1–4 shows the differential receiver input waveform. Figure 1–4. Receiver Input Waveform Single-Ended Waveform Positive Channel (p) Negative Channel (n) Ground Differential Waveform V ID (diff peak-peak) = 2 x V ID (single-ended) p −...
Page 469: Core Performance Specifications
Cyclone IV Devices. Clock Tree Specifications Table 1–24 lists the clock tree specifications for Cyclone IV devices. Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2) Performance Device Unit EP4CE6 437.5...
Page 470: Pll Specifications
— Note to Table 1–24: (1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. PLL Specifications Table 1–25 lists the PLL specifications for Cyclone IV devices when operating in the commercial junction temperature range (0°C to 85°C), the industrial junction temperature range (–40°C to 100°C), the extended industrial junction temperature...
Page 471 Chapter 1: Cyclone IV Device Datasheet 1–25 Switching Characteristics (1), (2) Table 1–25. PLL Specifications for Cyclone IV Devices (Part 2 of 2) Symbol Parameter Unit Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or — —...
Page 472: Embedded Multiplier Specifications
Configuration and Remote System Upgrades in Cyclone IV Devices chapter. (2) FPP configuration mode supports all Cyclone IV E devices (except for E144 package devices) and EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 only. (3) V = 1.0 V is only supported for Cyclone IV E 1.0 V core voltage devices.
Page 473: Periphery Performance
20 to 40 Note to Table 1–29: (1) AP configuration mode is only supported for Cyclone IV E devices. Table 1–30 lists the JTAG timing parameters and values for Cyclone IV devices. Table 1–30. JTAG Timing Parameters for Cyclone IV Devices...
Page 474 I/O timing for Cyclone IV devices. For definitions of high-speed timing specifications, refer to “Glossary” on page 1–37. (1), (2), Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (Part 1 of 2) C7, I7 C8, A7 C8L, I8L...
Page 475 LOCK (4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Page 476 Notes to Table 1–32: (1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX devices. (2) t is the time required for the PLL to lock from the end-of-device configuration.
Page 477 LOCK (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Page 478: External Memory Interface Specifications
LOCK (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Page 479: Duty Cycle Distortion Specifications
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Page 480: Ioe Programmable Delay
Table 1–41 list the IOE programmable delay for Cyclone IV E 1.0 V core voltage devices. (1), Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices Max Offset Number Parameter Paths Affected...
Page 481 Table 1–42 Table 1–43 list the IOE programmable delay for Cyclone IV E 1.2 V core voltage devices. (1), Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices Max Offset Number Paths Parameter...
Page 482 Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Table 1–44 Table 1–45 list the IOE programmable delay for Cyclone IV GX devices. (1), Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices Max Offset Number Paths Parameter Fast Corner Slow Corner...
Page 483: Glossary
Chapter 1: Cyclone IV Device Datasheet 1–37 I/O Timing I/O Timing Use the following methods to determine I/O timing: ■ the Excel-based I/O Timing ■ the Quartus II timing analyzer The Excel-based I/O timing provides pin timing performance for each device density and speed grade.
Page 484 1–38 Chapter 1: Cyclone IV Device Datasheet Glossary Table 1–46. Glossary (Part 2 of 5) Letter Term Definitions JPSU_TDI JPSU_TMS JTAG Waveform JPZX JPXZ JPCO JSSU Signal to be Captured JSZX JSCO JSXZ Signal to be Driven — — —...
Page 485 Table 1–46. Glossary (Part 3 of 5) Letter Term Definitions Receiver differential input discrete resistor (external to Cyclone IV devices). Receiver input waveform for LVDS and LVPECL differential standards: Single-Ended Waveform Positive Channel (p) = V Negative Channel (n) = V...
Page 486 1–40 Chapter 1: Cyclone IV Device Datasheet Glossary Table 1–46. Glossary (Part 4 of 5) Letter Term Definitions High-speed receiver and transmitter input and output clock period. Channel-to- High-speed I/O block: The timing difference between the fastest and slowest output edges,...
Page 487 Chapter 1: Cyclone IV Device Datasheet 1–41 Glossary Table 1–46. Glossary (Part 5 of 5) Letter Term Definitions DC common mode input voltage. CM(DC) AC differential input voltage: The minimum AC input differential voltage required for switching. DIF(AC) DC differential input voltage: The minimum DC input differential voltage required for switching.
Page 488: Document Revision History
Table 1–37, Table 1–38, Table 1–40, Table 1–42, and Table 1–43. March 2010 Added Table 1–5 to include ESD for Cyclone IV devices GPIOs and HSSI I/Os. ■ Added Table 1–44 and Table 1–45 to include IOE programmable delay for ■...
Page 489 Date Version Changes Updated Table 1–3 through Table 1–44 to include information for Cyclone IV E ■ devices and Cyclone IV GX devices for Quartus II software version 9.1 SP1 release. February 2010 Minor text edits. ■ November 2009 Initial release.
Page 490 1–44 Chapter 1: Cyclone IV Device Datasheet Document Revision History Cyclone IV Device Handbook, December 2016 Altera Corporation Volume 3...

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