Altera cyclone V Technical Reference page 967

cv_5v4
2016.10.28
The following list describes the CIU operation restrictions:
• After a command is issued, the CIU accepts another command only to check read status or to stop the
transfer.
• Only one data transfer command can be issued at a time.
• During an open-ended card write operation, if the card clock is stopped because the FIFO buffer is
empty, the software must first fill the data into the FIFO buffer and start the card clock. It can then issue
only an SD/SDIO STOP_TRANSMISSION (CMD12) command to the card.
• During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to
resume the suspended transfer, it must first reset the FIFO buffer and start the resume command as if it
were a new data transfer command.
• When issuing SD/SDIO card reset commands (GO_IDLE_STATE, GO_INACTIVE_STATE or
CMD52_reset) while a card data transfer is in progress, the software must set the stop abort command
bit (
stop_abort_cmd
issuing the card reset command.
• If the card clock is stopped because the FIFO buffer is full during a card read, the software must read at
least two FIFO buffer locations to start the card clock.
• If CE-ATA card device interrupts are enabled (the
new RW_BLK command must not be sent to the same card device if there is a pending RW_BLK
command in progress (the RW_BLK command used in this document is the RW_MULTIPLE_BLOCK
MMC command defined by the CE-ATA specification)​. Only the Command Completion Signal
Disable (CCSD) command can be sent while waiting for the Command Completion Signal (CCS).
• For the same card device, a new command is allowed for reading status information, if interrupts are
disabled in the CE-ATA card (the
• Open-ended transfers are not supported for the CE-ATA card devices.
• The
send_auto_stop
register) for CE-ATA transfers.
The CIU consists of the following primary functional blocks:
• Command path
• Data path
• Clock control
Command Path
The command path performs the following functions:
• Load card command parameters
• Send commands to card bus
• Receive responses from card bus
• Send responses to BIU
• Load clock parameters
• Drives the P-bit on command pin
A new command is issued to the controller by writing to the BIU registers and setting the
the register. The command path loads the new command (command, command argument, timeout)
cmd
and sends an acknowledgement to the BIU.
After the new command is loaded, the command path state machine sends a command to the card bus—
including the internally generated seven-term CRC (CRC-7)—and receives a response, if any. The state
machine then sends the received response and signals to the BIU that the command is done, and then
waits for eight clock cycles before loading a new command. In CE-ATA data payload transfer
(RW_MULTIPLE_BLOCK) commands, if the card device interrupts are enabled (the nIEN bit is set to 0
SD/MMC Controller
Send Feedback
†
) in the
cmd
†
signal is not supported (software must not set the
†
†
†
†
†
†
†
†
†
†
†
†
register to 1 so that the controller can stop the data transfer after
†
bit is set to 0 in the ATA control register), a
nIEN
bit is set to 1 in the ATA control register).
nIEN
†
†
†
†
Command Path
†
†
†
bit in the
send_auto_stop
start_cmd
Altera Corporation
14-21
†
cmd
bit in