Altera cyclone V Technical Reference page 782

11-44
SDRAM Controller Module Register Descriptions
dramodt
on page 11-52
This register controls which
with chip select 1 (CS1) assertion.
dramaddrw
This register configures the width of the various address fields of the DRAM. The values specified in this
register must match the memory devices being used.
dramifwidth
This register controls the interface width of the SDRAM controller.
dramsts on page 11-55
This register provides the status of the calibration and ECC logic.
dramintr
This register can enable, disable and clear the SDRAM error interrupts.
sbecount on page 11-57
This register tracks the single-bit error count.
dbecount
This register tracks the double-bit error count.
erraddr
on page 11-58
This register holds the address of the most recent ECC error.
dropcount
This register holds the address of the most recent ECC error.
dropaddr
This register holds the last dropped address.
lowpwreq
This register instructs the controller to put the DRAM into a power down state. Note that some commands
are only valid for certain memory types.
lowpwrack
This register gives the status of the power down commands requested by the Low Power Control register.
staticcfg on page 11-62
This register controls configuration values which cannot be updated during active transfers. First configure
the
membl
write only.
ctrlwidth
This register controls the width of the physical DRAM interface.
portcfg on page 11-64
Each bit of the
memory accesses, the corresponding
then its
autopchen
fpgaportrst
This register implements functionality to allow the CPU to control when the MPFE will enable the ports to
the FPGA fabric.
Altera Corporation
pin asserts with chip select 0 (CS0) assertion and which
ODT
on page 11-53
on page 11-54
on page 11-56
on page 11-58
on page 11-59
on page 11-60
on page 11-60
on page 11-61
and fields and then re-write these fields while setting the applycfg bit. The applycfg bit is
eccn
on page 11-63
field maps to one of the control ports. If a port executes mostly sequential
autopchen
bit should be set to 1.
on page 11-66
bit should be 0. If the port has highly random accesses,
autopchen
cv_5v4
2016.10.28
pin asserts
ODT
SDRAM Controller Subsystem
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