L2 Cache Controller Address Map - Altera cyclone V Technical Reference

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L2 Cache Controller Address Map

Related Information
Cortex-A9 MPCore Technical Reference Manual
For more information about the use of the MPU address space, refer to the Cortex-A9 MPCore Technical
Reference Manual, available on the ARM Infocenter website.
L2 Cache Controller Address Map
The register space for the L2 cache controller ranges from 0xFFEF000 to 0xFFFEFFFF.
Table 9-17: MPU L2 Cache Controller Address Range
Module Instance
MPUL2
Table 9-18: MPU L2 Cache Controller Register Range
Register Group
Cache ID and Cache
Type
Control
Interrupt/Counter
Control
Reserved
Cache Maintenance
Operations
Reserved
Cache Lockdown
Reserved
Altera Corporation
0xFFFEF000
Description
This address space is
allocated for the cache
ID and cache type
registers.
This is the address
space for the cache
control registers.
This address space is
allocated for the
Interrupt/Counter
control registers.
This address space is
reserved.
This is the address
space is allocated for
the cache maintenance
operation registers.
This address space is
reserved.
This address space is
allocated for cache
lockdown registers.
This address space is
reserved.
Start Address
Start Address
0xFFFEF000
0xFFFEF100
0xFFFEF200
0xFFFEF300
0xFFFEF700
0xFFFEF800
0xFFFEF900
0xFFFEFA00
End Address
0xFFFEFFFF
End Address
0xFFFEF0FF
0xFFFEF1FF
0xFFFEF2FF
0xFFFEF6FF
0xFFFEF7FF
0xFFFEF8FF
0xFFFEF9FF
0xFFFEFBFF
Cortex-A9 Microprocessor Unit Subsystem
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cv_5v4
2016.10.28