Functional Description Of Coresight Debug And Trace - Altera cyclone V Technical Reference

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Functional Description of CoreSight Debug and Trace

Functional Description of CoreSight Debug and Trace
Debug Access Port
The Debug Access Port (DAP) provides the necessary ports for a host debugger to connect to and
communicate with the HPS through a JTAG interface connected to dedicated HPS pins that is
independent of the JTAG for the FPGA. The JTAG interface provided with the DAP allows a host debugger
to access various modules inside the HPS. Additionally, a debug monitor executing on either processor can
access different HPS components by interfacing with the system Advanced Microcontroller Bus Architec‐
ture (AMBA) Advanced Peripheral Bus (APB) slave port of the DAP.
The system APB slave port occupies 2 MB of address space in the HPS. Both the JTAG port and system
APB port have access to the debug APB master port of the DAP.
A host debugger can access any HPS memory-mapped resource in the system through the DAP system
master port. Requests made over the DAP system master port are impacted by reads and writes to
peripheral registers.
Note: The HPS JTAG interface does not support boundary scan tests (BST). To perform boundary scan
testing on HPS I/Os, use the FPGA JTAG pins.
Related Information
CoreSight Debug and Trace Block Diagram and System Integration
•
Shows CoreSight components connected to the debug APB
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
•
For more information about boundary scan tests, refer to the "JTAG Boundary-Scan Testing in Cyclone
V Devices" chapter.
• Scan Manager
ARM Infocenter
•
Refer to the CoreSight Components Technical Reference Manual on the ARM Infocenter website.
System Trace Macrocell
The STM allows messages to be injected into the trace stream for delivery to the host debugger receiving
the trace data. These messages can be sent through stimulus ports or the hardware EVENT interface. The
STM allows these messages to be time stamped.
The STM provides an AMBA Advanced eXtensible Interface (AXI) slave interface used to create trace
events. The interface can be accessed by the MPU subsystem, direct memory access (DMA) controller, and
masters implemented as soft logic in the FPGA fabric through the FPGA-to-HPS bridge. The AXI slave
interface supports three address segments, where each address segment is 16 MB and each segment
supports up to 65536 channels. Each channel occupies 256 bytes of address space.
The STM also provides 32 hardware EVENT pins. The higher-order 28 pins (31:4) are connected to the
FPGA fabric, allowing logic inside FPGA to insert messages into the trace stream. When the STM detects
a rising edge on an EVENT pin, a message identifying the EVENT is inserted into the stream. The lower
four EVENT pins (3:0) are connected to csCTI.
Related Information
HPS-FPGA Bridges
•
Altera Corporation
on page 6-1
on page 8-1
on page 10-3
CoreSight Debug and Trace
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2016.10.28