Altera cyclone V Technical Reference page 267

cv_5v4
2016.10.28
Bit
1
hprotdata_1
0
hprotdata_0
ECC Management Register Group Register Descriptions
ECC error status and control for all ECC-protected HPS RAM blocks.
Offset:
0x140
l2
on page 5-74
This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path
using bits in this register. This register is reset by a cold reset (ignores warm reset). The interrupt status of
the L2 ECC single/double bit error is handled in the General Interrupt Controller (GIC).
ocram
on page 5-75
This register is used to enable ECC on the On-chip RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
usb0 on page 5-76
This register is used to enable ECC on the USB0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
usb1 on page 5-77
This register is used to enable ECC on the USB1 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
emac0 on page 5-78
This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
System Manager
Send Feedback
Name
Specifies if the L3 master access is for data or opcode
for the USB modules. The field array index
corresponds to the USB index.
Value
0x0
0x1
Specifies if the L3 master access is for data or opcode
for the USB modules. The field array index
corresponds to the USB index.
Value
0x0
0x1
ECC Management Register Group Register Descriptions
Description
Description
Opcode fetch
Data access
Description
Opcode fetch
Data access
5-73
Access Reset
RW 0x1
RW 0x1
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