Altera cyclone V Technical Reference page 608

8-26
comp_id_1
comp_id_0 Fields
Bit
7:0
preamble
comp_id_1
Component ID1
Module Instance
hps2fpgaregs
Offset:
0x1FF4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_1 Fields
Bit
7:0
genipcompcls_preamble
comp_id_2
Component ID2
Module Instance
hps2fpgaregs
Offset:
0x1FF8
Access:
RO
Altera Corporation
Name
Preamble
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Generic IP component class, Preamble
Description
Base Address
0xFF500000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF500000
Access
Register Address
0xFF501FF4
21 20 19 18
5 4 3 2
genipcompcls_preamble
RO 0xF0
Access
Register Address
0xFF501FF8
cv_5v4
2016.10.28
Reset
RO 0xD
17 16
1 0
Reset
RO 0xF0
HPS-FPGA Bridges
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