Altera cyclone V Technical Reference page 454

7-6
Available Address Maps
Figure 7-4: Address Maps for System Interconnect Masters
Notes on Address Maps
(1)
Transactions on these addresses are directly decoded by the SCU and L2 cache.
(2)
This region can be configured to access slaves on the lightweight HPS-to-FPGA bridge, by using the
register.
remap
(3)
This region can be configured to access slaves on the HPS-to-FPGA bridge, by using the
(4)
The MPU accesses SDRAM through a dedicated port.
(5)
This region can be configured to access on-chip RAM, by using the
Altera Corporation
DMA Peripherals (6)
0xFFFFFFFF
On-Chip RAM On-Chip RAM
0xFFFF0000
0xFFFEC000
0xFFFD0000
Peripherals
and L3 GPV
0xFF400000
LW H-to-F (2)
0xFF200000
DAP
0xFF000000
STM
0xFC000000
H-to-F (3)
0xC0000000
ACP
0x80000000
SDRAM
0x00100000
0x00010000
SDRAM (5)
0x00000000
Master FPGA-to-HPS
DAP
On-Chip RAM On-Chip RAM
Peripherals Peripherals
and L3 GPV and L3 GPV
LW H-to-F (2) LW H-to-F (2)
DAP
H-to-F (3) H-to-F (3)
ACP ACP
SDRAM SDRAM
SDRAM (5) SDRAM (5)
Bridge MPU
On-Chip RAM
SCU and L2
Registers (1)
Boot ROM
Peripherals
and L3 GPV
LW H-to-F (2)
DAP DAP
STM STM
H-to-F (3)
ACP
SDRAM (4)
SDRAM
SDRAM (5) Boot ROM
register.
remap
System Interconnect
cv_5v4
2016.10.28
register.
remap
Send Feedback