Altera cyclone V Technical Reference page 166

cv_5v4
2016.10.28
• nSTATUS - Driven to 0 by the FPGA in this device if the FPGA is in Reset Phase or if the FPGA
detected an error during the Configuration Phase.
• CONF_DONE - Driven to 0 by the FPGA in this device during the Reset Phase and driven to 1 when
the FPGA Configuration Phase is done.
• INIT_DONE - Driven to 0 by the FPGA in this device during the Configuration Phase and driven to 1
when the FPGA Initialization Phase is done.
• CRC_ERROR - CRC error indicator. A CRC_ERROR value of 1 indicates that the FPGA detected a
CRC error while in User Mode.
• CVP_CONF_DONE - Configuration via PCIe done indicator. A CVP_CONF_DONE value of 1
indicates that CVP is done.
• PR_READY - Partial reconfiguration ready indicator. A PR_READY value of 1 indicates that the FPGA
is ready to receive partial reconfiguration or external scrubbing data.
• PR_ERROR - Partial reconfiguration error indicator. A PR_ERROR value of 1 indicates that the FPGA
detected an error during partial reconfiguration or external scrubbing.
• PR_DONE - Partial reconfiguration done indicator. A PR_DONE value of 1 indicates partial reconfi‐
guration or external scrubbing is done.
• nCONFIG Pin - Value of the nCONFIG pin. This can be pulled-down by the FPGA in this device or
logic external to this device connected to the nCONFIG pin. See the description of the nCONFIG field
in this register to understand when the FPGA in this device pulls-down the nCONFIG pin. Logic
external to this device pulls-down the nCONFIG pin to put the FPGA into the Reset Phase.
• nSTATUS Pin - Value of the nSTATUS pin. This can be pulled-down by the FPGA in this device or
logic external to this device connected to the nSTATUS pin. See the description of the nSTATUS field
in this register to understand when the FPGA in this device pulls-down the nSTATUS pin. Logic
external to this device pulls-down the nSTATUS pin during Configuration Phase or Initialization Phase
if it detected an error.
• CONF_DONE Pin - Value of the CONF_DONE pin. This can be pulled-down by the FPGA in this
device or logic external to this device connected to the CONF_DONE pin. See the description of the
CONF_DONE field in this register to understand when the FPGA in this device pulls-down the
CONF_DONE pin. See FPGA documentation to determine how logic external to this device drives
CONF_DONE.
• FPGA_POWER_ON - FPGA powered on indicator
• 0 = FPGA portion of device is powered off.
• 1 = FPGA portion of device is powered on.
Offset:
0x800
gpio_inten
Allows each bit of Port A to be configured to generate an interrupt or not.
gpio_intmask
This register has 12 individual interrupt masks for the MON. Controls whether an interrupt on Port A can
create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are
unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for
this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the
resultant status after masking.
gpio_inttype_level
The interrupt level register defines the type of interrupt (edge or level) for each GPIO input.
FPGA Manager
Send Feedback
on page 4-24
on page 4-27
on page 4-30
Configuration Monitor (MON) Registers Register Descriptions
4-23
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