Xip Mode - Altera cyclone V Technical Reference

15-12

XIP Mode

XIP Mode
The quad SPI controller supports XIP mode, if the flash devices support XIP mode. Depending on the
flash device, XIP mode puts the flash device in read-only mode, reducing command overhead.
The quad SPI controller must instruct the flash device to enter XIP mode by sending the mode bits. When
the enter XIP mode on next read bit (
controller and the flash device are ready to enter XIP mode on the next read instruction. When the enter
XIP mode immediately bit (
device enter XIP mode immediately.
When the
flash device exit XIP mode on the next read instruction. For more information, refer to the "XIP Mode
Operations" section.
Related Information
XIP Mode Operations
Write Protection
You can program the controller to write protect a specific region of the flash device. The protected region
is defined as a set of blocks, specified by a starting and ending block. Writing to an area of protected flash
region memory generates an error and triggers an interrupt.
You define the block size by specifying the number of bytes per block through the number of bytes per
block field (
(
lowwrprot
(
uppwrprot
The write protection enable bit (
protection. The write protection inversion bit (
so that the region specified by
region is protected.
Data Slave Sequential Access Detection
The quad SPI flash controller detects sequential accesses to the data slave interface by comparing the
current access with the previous access. An access is sequential when it meets the following conditions:
• The address of the current access sequentially follows the address of the previous access.
• The direction of the current access (read or write) is the same as previous access.
• The size of the current access (byte, half-word, or word) is the same as previous access.
When the access is detected as nonsequential, the sequential access to the flash device is terminated and a
new sequential access begins. Altera recommends accessing the data slave sequentially. Sequential access
has less command overhead, and therefore, increases data throughput.
Clocks
There are two clock inputs to the quad SPI controller:
output:
qspi_clk
and register slave accesses. The
is used to serialize the data and drive the external SPI interface. The
the connected flash devices.
The following is true for the following reference clocks:
Altera Corporation
enterxipimm
or
enterxipnextrd enterxipimm
on page 15-17
) of the device size register (
bytespersubsector
) specifies the first flash block in the protected region. The upper write protection register
) specifies the last flash block in the protected region.
) of the write protection register (
en
lowwrprt
. The quad SPI flash controller uses the
qspi_ref_clk
) of the
enterxipnextrd
) of the register is set to 1, the quad SPI controller and flash
cfg
bit of the register is set to 0, the quad SPI controller and
cfg
devsz
) of the
inv wrprot
and is unprotected and all flash memory outside that
uppwrprt
l4_mp_clk
l4_mp_clk
clock is the reference clock for the quad SPI controller and
register is set to 1, the quad SPI
cfg
). The lower write protection register
) enables and disables write
wrprot
register flips the definition of protection
and ; and one clock
qspi_ref_clk
clock to clock the data slave transfers
clock is the clock source for
qspi_clk
Quad SPI Flash Controller
cv_5v4
2016.10.28
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