Altera cyclone V Technical Reference page 170

cv_5v4
2016.10.28
Bit
0
ns
gpio_intmask
This register has 12 individual interrupt masks for the MON. Controls whether an interrupt on Port A can
create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are
unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for
this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the
resultant status after masking.
Module Instance
fpgamgrregs
Offset:
0x834
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
FPGA Manager
Send Feedback
Name
Enables interrupt generation for nSTATUS
Value
0x0
0x1
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
fpo cdp
RW RW
0x0 0x0
Description
Description
Disable Interrupt
Enable Interrupt
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RW RW RW RW
0x0 0x0 0x0 0x0
gpio_intmask
Access
Register Address
0xFF706834
21 20 19 18
5 4 3 2
prr ccd crc id
RW RW RW RW
0x0 0x0 0x0 0x0
4-27
Reset
RW 0x0
17 16
1 0
cd ns
RW RW 0x0
0x0
Altera Corporation