Altera cyclone V Technical Reference page 676

9-40
vid3rd
Module Instance
acpidmap
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
force Reserved
RW 0x1
15 14
Reserved
vid2wr Fields
Bit
31
force
27:16
mid
13:12
page
8:4
user
vid3rd
The Read AXI Master Mapping Register contains the USER, ADDR page, and ID signals mapping values
for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID.
Module Instance
acpidmap
Offset:
0x8
Access:
RW
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
page Reserved
RW 0x0
Name
Set to 1 to force the mapping between the 12-bit ID
and 3-bit virtual ID N. Set to 0 to allow the 3-bit ID N
to be dynamically allocated.
The 12-bit ID of the master to remap to 3-bit virtual
ID N, where N is the 3-bit ID to use.
AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB
memory region.
This value is propagated to SCU as AWUSERS.
Base Address
0xFF707000
Bit Fields
25 24 23 22
9 8 7 6
user
RW 0x1
Description
Base Address
0xFF707000
Register Address
0xFF707004
21 20 19 18
mid
RW 0x4
5 4 3
Register Address
0xFF707008
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
17 16
2 1 0
Reserved
Access Reset
RW 0x1
RW 0x4
RW 0x0
RW 0x1
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