Phy Management Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

PHY Management Interface

The HPS can provide support for either MDIO or I
MDIO Interface
The MDIO interface signals are synchronous to
Note: The MDIO interface signals can be routed to both the FPGA and HPS I/O.
Table 17-3: PHY MDIO Management Interface
Signal
emac_gmii_mdi_i
emac_gmii_mdo_o
emac_gmii_mdo_o_e
emac_gmii_mdc_o
2
I C External PHY Management Interface
Some PHY devices use the I
(SFP) optical or pluggable modules are often among those with this interface.
The HPS or FPGA can use two of the four general purpose I
devices:
• I2C2 at base address 0xFFC06000
• I2C3 at base address 0xFFC07000
Ethernet Media Access Controller
Send Feedback
l4_mp_clk
In/Out Width
In 1 Management Data In. The PHY generates this signal to
transfer register data during a read operation. This
signal is driven synchronously with the
clock.
Out 1 Management Data Out. The EMAC uses this signal to
transfer control and data information to the PHY.
Out 1 Management Data Output Enable. This enable signal
drives the
state I/O buffer. This signal is asserted whenever valid
data is driven on the
state of this signal is high.
Out 1 Management Data Clock. The EMAC provides timing
reference for the
on MII through this aperiodic clock. The maximum
frequency of this clock is 2.5 MHz. This clock is
generated from the application clock through a clock
divider.
2
C instead of MDIO for their control interface. Small form factor pluggable
PHY Management Interface
2
C PHY management interfaces.
in all supported modes.
Description
signal from an external three-
gmii_mdo_o
gmii_mdo_o
gmii_mdi_i
2
C peripherals for controlling the PHY
17-11
gmii_mdc_o
signal. The active
and signals
gmii_mdo_o
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