Altera cyclone V Technical Reference page 914

cv_5v4
2016.10.28
Bit
5:4
value2
3:2
value1
1:0
value0
intr_status0
Interrupt status register for bank 0
Module Instance
nandregs
Offset:
0x410
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
page_ pipe_ rst_
xfer_inc cmd_ comp
err
RW 0x0
RW 0x0
0x0
intr_status0 Fields
Bit
15
page_xfer_inc
NAND Flash Controller
Send Feedback
Name
[list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is
in Spare mode [*]10 - Bank 2 is in Main+Spare
mode[/list]
[list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is
in Spare mode [*]10 - Bank 1 is in Main+Spare
mode[/list]
[list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is
in Spare mode [*]10 - Bank 0 is in Main+Spare
mode[/list]
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
INT_ unsup locke
act _cmd d_blk
RW RW RW RW
0x0 0x0 0x0
Name
For every page of data transfer to or from the device,
this bit will be set.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
pipe_ erase progr load_
cpybc _comp am_ comp
k_ comp
RW RW
cmd_
0x0 RW 0x0
comp
0x0
RW
0x0
Description
intr_status0
Access
Register Address
0xFFB80410
21 20 19 18
5 4 3 2
erase progr time_ dma_
_fail am_ out cmd_
fail comp
RW RW
0x0 RW 0x0 RW
0x0 0x0
Access
13-93
Reset
RO 0x0
RO 0x0
RO 0x0
17 16
1 0
Reser ecc_
ved uncor_
err
RW 0x0
Reset
RW 0x0
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