Altera cyclone V Technical Reference page 892

cv_5v4
2016.10.28
cs_setup_cnt
Chip select setup time
Module Instance
nandregs
Offset:
0x220
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
cs_setup_cnt Fields
Bit
4:0
value
spare_area_skip_bytes
Spare area skip bytes
Module Instance
nandregs
Offset:
0x230
Access:
RW
NAND Flash Controller
Send Feedback
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Number of nand_mp_clk cycles required for meeting
chip select setup time. This register refers to device
timing parameter Tcs. The value in this registers
reflects the extra setup cycles for chip select before
read/write enable signal is set low. The default value is
calculated for ONFI Timing mode 0 Tcs = 70ns and
maximum nand_mp_clk period of 4ns for 1x/4x clock
multiple for 16ns cycle time device.
0xFFB80000
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
cs_setup_cnt
Register Address
0xFFB80220
21 20 19 18
5 4 3 2
value
RW 0x3
Access
Register Address
0xFFB80230
13-71
17 16
1 0
Reset
RW 0x3
Altera Corporation