Altera cyclone V Technical Reference page 100

cv_5v4
2016.10.28
stat Fields
Bit
5:0
outresetack
SDRAM PLL Group Register Descriptions
Contains registers with settings for the SDRAM PLL.
Offset:
0xc0
vco
on page 2-64
Contains settings that control the SDRAM PLL VCO. The VCO output frequency is the input frequency
multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold
reset.
ctrl
on page 2-66
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
ddrdqsclk
Contains settings that control clock ddr_dqs_clk generated from the C0 output of the SDRAM PLL. Fields
are only reset by a cold reset.
ddr2xdqsclk
Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output of the SDRAM PLL.
Fields are only reset by a cold reset.
ddrdqclk
on page 2-69
Contains settings that control clock ddr_dq_clk generated from the C2 output of the SDRAM PLL. Fields
are only reset by a cold reset.
s2fuser2clk
Contains settings that control clock s2f_user2_clk generated from the C5 output of the SDRAM PLL. Qsys
and user documenation refer to s2f_user2_clk as h2f_user2_clk Fields are only reset by a cold reset.
Clock Manager
Send Feedback
Name
These read only bits per PLL output indicate that the
PLL has received the Output Reset Counter request
and has gracefully stopped the respective PLL output
clock. For software to change the PLL output counter
without producing glitches on the respective clock,
SW must set the VCO register respective Output
Counter Reset bit. Software then polls the respective
Output Counter Reset Acknowledge bit in the Output
Counter Reset Ack Status Register. Software then
writes the appropriate counter register, and then
clears the respective VCO register Output Counter
Reset bit. The reset value of this bit is applied on a
cold reset; warm reset has no effect on this bit.
Value
0x0
0x1
on page 2-67
on page 2-68
on page 2-70
SDRAM PLL Group Register Descriptions
Description
Description
Idle
Output Counter Acknowledge received.
2-63
Access Reset
RO 0x0
Altera Corporation