Altera cyclone V Technical Reference page 457

cv_5v4
2016.10.28
On-Chip RAM Region
The on-chip RAM is always mapped (independent of the boot region contents).
Related Information
Bit Fields for Modifying the Memory Map
•
Cortex-A9 Microprocessor Unit Subsystem
•
For general information about the MPU subsystem, refer to the Cortex-A9 Microprocessor Unit
Subsystem chapter.
MPU Address Space
The MPU address space is 4 GB and applies to MPU masters.
Addresses generated by the MPU are decoded in three ways:
• By default, MPU accesses to locations between 0x100000 (1 MB) to 0xC0000000 (3 GB) are made to
the SDRAM controller.
• Addresses in the SCU and L2 register region (0xFFFEC000 to 0xFFFF0000) are the SCU and L2 bus.
• Accesses to all other locations are made to the L3 interconnect.
The MPU L2 cache controller contains a master connected to the system interconnect and a master
connected to the SDRAM.
The MPU address space contains the following regions:
Table 7-2: MPU Default Address Space Regions
Description
Boot ROM
SDRAM window Always visible
HPS-to-FPGA
System trace
macrocell
Debug access
port
Lightweight HPS-
to-FPGA
Peripherals
Boot ROM
(15) For details about the
System Interconnect
Send Feedback
Condition
Always visible
0x00000000
0x00100000
When 0xC0000000
(15)
remap.hps2fpga
is set.
Always visible 0xFC000000
Always visible 0xFF000000
Visible when 0xFF200000
(15)
remap.hps2fpga
is set.
Always visible 0xFF400000
Always visible 0xFFFD0000
register, refer to "Bit Fields for Modifying the Memory Map"
remap
on page 7-12
on page 9-1
End Address
Base Address
0x000FFFFF
0xBFFFFFFF
0xFBFFFFFF
0xFFEFFFFF
0xFF1FFFFF
0xFF3FFFFF
0xFFFCFFFF
0xFFFEBFFF
7-9
MPU Address Space
Size
1 MB
3047 MB (3 GB –
1 MB)
348 KB
48 KB
2 MB
2 MB
12096 KB
112 KB
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