Altera cyclone V Technical Reference page 617

cv_5v4
2016.10.28
Signal
ARLOCK
ARCACHE
ARPROT
ARVALID
ARREADY
Table 8-14: Lightweight HPS-to-FPGA Bridge Master Read Data Channel Signals
Signal
RID
RDATA
RRESP
RLAST
RVALID
RREADY
LWHPS2FPGA AXI Bridge Module Address Map
Registers in the LWHPS2FPGA AXI Bridge Module.
Base Address:
ID Register Group
Register
periph_id_4 on page
8-37
periph_id_0 on page
8-38
periph_id_1 on page
8-38
periph_id_2 on page
8-39
HPS-FPGA Bridges
Send Feedback
Width Direction
2 bits Output
4 bits Output
3 bits Output
1 bit Output
1 bit Input
Width Direction
12 bits Input
32 bits Input
2 bits Input
1 bit Input
1 bit Input
1 bit Output
0xFF400000
Offset Width Acces
0x1FD0
0x1FE0
0x1FE4
0x1FE8
LWHPS2FPGA AXI Bridge Module Address Map
Lock type—Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Read address channel valid
Read address channel ready
Read ID
Read data
Read response
Read last data identifier
Read data channel valid
Read data channel ready
Reset Value
s
32 RO 0x4
32 RO 0x1
32 RO 0xB3
32 RO 0x6B
Description
Description
Description
Peripheral ID4 Register
Peripheral ID0 Register
Peripheral ID1 Register
Peripheral ID2 Register
Altera Corporation
8-35