Altera cyclone V Technical Reference page 456

7-8
L3 Address Space
Description
System trace macrocell
Debug access port
Lightweight HPS-to-
FPGA
Peripherals
On-chip RAM
The boot ROM and internal MPU registers (SCU and L2) are not accessible to L3 masters.
SDRAM Window Region
The SDRAM window region is 3 GB and provides access to the bottom 3 GB of the SDRAM address space.
Any L3 master can access a cache-coherent view of SDRAM by performing a cacheable access through the
ACP.
On-Chip RAM Region
The system interconnect
0x0 is mapped to the on-chip RAM or the SDRAM. The SDRAM is mapped to address 0x0 on reset.
ACP Window Region
The ACP window region is 1 GB and provides access to a configurable gigabyte-aligned region of the MPU
address space. Registers in the ACP ID mapper control which gigabyte-aligned region of the MPU address
space is accessed by the ACP window region. The ACP window region is used by L3 masters to perform
coherent accesses into the MPU address space. For more information about the ACP ID mapper, refer to
the Cortex-A9 Microprocessor Unit Subsystem chapter.
HPS-to-FPGA Slaves Region
The HPS-to-FPGA slaves region provides access to 960 MB of slaves in the FPGA fabric through the HPS-
to-FPGA bridge.
Lightweight HPS-to-FPGA Slaves Region
The lightweight HPS-to-FPGA slaves provide access to slaves in the FPGA fabric through the lightweight
HPS-to-FPGA bridge.
Peripherals Region
The peripherals region includes slaves connected to the L3 interconnect and L4 buses.
Altera Corporation
Condition
Always visible to DMA and
FPGA-to-HPS
Not visible to master
peripherals. Always visible
to other masters.
Not visible to master
peripherals. Visible to other
masters when
(14) is set.
remap.hps2fpga
Not visible to master
peripherals. Always visible
to other masters.
Always visible
register, in the
remap l3regs
Base Address End Address
0xFC000000 0xFEFFFFFF 48 KB
0xFF000000 0xFF1FFFFF 2 MB
0xFF200000 0xFF3FFFFF 2 MB
0xFF400000 0xFFFCFFFF 12096 KB
0xFFFF0000 0xFFFFFFFF 64 KB
group, determines if the 64 KB starting at address
cv_5v4
2016.10.28
Size
System Interconnect
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