Cortex-A9 Mpu Subsystem Block Diagram And System Integration - Altera cyclone V Technical Reference

9-2

Cortex-A9 MPU Subsystem Block Diagram and System Integration

Cortex-A9 MPU Subsystem Block Diagram and System Integration
Cortex-A9 MPU Subsystem with System Interconnect
This block diagram shows a dual-core MPU subsystem in the context of the HPS, with the L2 cache. The
L2 cache can access either the system interconnect or the SDRAM.
Figure 9-1: Cortex-A9 MPU Subsystem with Interconnect Block Diagram
Altera Corporation
System
Interconnect
MPU Subsystem
ARM Cortex-A9 MPCore
CPU0
ACP ID
ACP
SCU
Mapper
L2 Cache
M0
M1
SDRAM
Controller
Subsystem
Interrupts
CPU1
Debug Infrastructure
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
Send Feedback