Altera cyclone V Technical Reference page 62

cv_5v4
2016.10.28
Register
l4src on page 2-46
stat on page 2-47
Peripheral PLL Group
Register
vco on page 2-49
misc on page 2-51
emac0clk on page 2-
52
emac1clk on page 2-
53
perqspiclk on page 2-
53
pernandsdmmcclk
page 2-54
perbaseclk on page 2-
55
s2fuser1clk on page
2-55
en on page 2-56
div on page 2-57
gpiodiv on page 2-60
src on page 2-61
stat on page 2-62
Clock Manager
Send Feedback
Offset Width Acces
0x70 32
0x74 32
Offset Width Acces
0x80 32
0x84 32
0x88 32
0x8C 32
0x90 32
on 0x94 32
0x98 32
0x9C 32
0xA0 32
0xA4 32
0xA8 32
0xAC 32
0xB0 32
Clock Manager Module Address Map
Reset Value
s
L4 MP SP APB Clock Source
RW 0x0
Main PLL Output Counter Reset
RO 0x0
Ack Status Register
Reset Value
s
Peripheral PLL VCO Control
RW 0x8001000D
Register
Peripheral PLL VCO Advanced
RW 0x4002
Control Register
Peripheral PLL C0 Control
RW 0x1
Register for Clock emac0_clk
Peripheral PLL C1 Control
RW 0x1
Register for Clock emac1_clk
Peripheral PLL C2 Control
RW 0x1
Register for Clock periph_qspi_
clk
Peripheral PLL C3 Control
RW 0x1
Register for Clock periph_nand_
sdmmc_clk
Peripheral PLL C4 Control
RW 0x1
Register for Clock periph_base_
clk
Peripheral PLL C5 Control
RW 0x1
Register for Clock s2f_user1_clk
Enable Register
RW 0xFFF
Divide Register
RW 0x0
GPIO Divide Register
RW 0x1
Flash Clock Source Register
RW 0x15
Peripheral PLL Output Counter
RO 0x0
Reset Ack Status Register
2-25
Description
Description
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