Reset Controller - Altera cyclone V Technical Reference

3-4

Reset Controller

Table 3-2: HPS External Reset Sources
f2h_cold_rst_req_n
f2h_warm_rst_req_n
f2h_dbg_rst_req_n
h2f_cold_rst_n
h2f_rst_n
h2f_dbg_rst_n
load_csr
nPOR
nRST
and
nRST nPOR
information on
Related Information
Cyclone V Device Datasheet
For information about the required duration of reset request signal assertion, refer to the Cyclone V
Device Datasheet.
Reset Controller
The reset controller performs the following functions:
• Accepts reset requests from the FPGA CB, FPGA fabric, modules in the HPS, and reset pins
• Generates an individual reset signal for each module instance for all modules in the HPS
• Provides reset handshaking signals to support system reset behavior
The reset controller generates module reset signals from external reset requests and internal reset requests.
External reset requests originate from sources external to the reset manager. Internal reset requests
originate from control registers in the reset manager.
The reset controller supports the following cold reset requests:
• Power-on reset (POR) voltage monitor
• Cold reset request pin (
• FPGA fabric
• FPGA CB and scan manager
• Software cold reset request bit (
Altera Corporation
Source
are powered by the HPS reset and clock input pins power supply (
, refer to the Cyclone V Device Datasheet.
V _HPS
CCRSTCLK
)
nPOR
swcoldrstreq
Cold reset request from FPGA fabric (active low)
Warm reset request from FPGA fabric (active low)
Debug reset request from FPGA fabric (active low)
Cold-only reset to FPGA fabric (active low)
Cold or warm reset to FPGA fabric (active low)
Debug reset (
dbg_rst_n
Cold-only reset from FPGA control block (CB) and scan
manager
Power-on reset pin (active low)
Warm reset pin (active low)
) of the control register (
Description
) to FPGA fabric (active low)
V
CCRSTCLK
)
ctrl
cv_5v4
2016.10.28
). For more
_HPS
Reset Manager
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