Resets - Altera cyclone V Technical Reference

14-36

Resets

Figure 14-10: SD/MMC Controller Clock Connections
l4_mp_clk
sdmmc_clk
The
sdmmc_clk
clock before passing to the phase shifters and the SD/MMC controller CIU. The phase shifters are used to
generate the
phases shift which include 0, 45, 90, 135, 180, 225, 270, and 315 degrees. The
be driven by the output from the phase shifter.
Note: The selections of phase shift degree and
For information about setting the phase shift and selecting the source of the
clock, refer to the "Clock Setup" section within this document.
The controller generates the
about the generation of the
document.
Related Information
Clock Setup
•
Refer to this section for information about setting the phase shift.
Clock Control Block
•
Refer to this section for information about the generation of the
Resets
The SD/MMC controller has one reset signal. The reset manager drives this signal to the SD/MMC
controller on a cold or warm reset.
Related Information
Reset Manager
Taking the SD/MMC Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
Altera Corporation
Divide
by 4
clock from the clock manager is divided by four and becomes the
and
sdmmc_drv_clk sdmmc_sample_clk
sdmmc_cclk_out
sdmmc_cclk_out
on page 14-46
on page 14-33
on page 3-1
sdmmc_clk_divided
sdmmc_drv_clk
Phase
Shifter
sdmmc_sample_clk
clocks. These phase shifters provide up to eight
sdmmc_sample_clk
clock, which is driven to the card. For more information
clock, refer to the "Clock Control Block" section within this
sdmmc_cclk_out
SD/MMC
Controller
Core
sdmmc_clk_divided
sdmmc_sample_clk
source are done in the system manager.
sdmmc_sample_clk
clock.
sdmmc_cclk_out
SD/MMC Controller
cv_5v4
2016.10.28
clock can
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