Features Of The System Interconnect - Altera cyclone V Technical Reference

2016.10.28
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The components of the hard processor system (HPS) communicate with one another, and with other
portions of the SoC device, through the system interconnect. The system interconnect consists of the
following blocks:
• The main level 3 (L3) interconnect
• The level 4 (L4) buses
The system interconnect is implemented with the ARM CoreLink
NIC-301 provides a foundation for a high-performance HPS system interconnect based on the ARM
Advanced Microcontroller Bus Architecture (AMBA
High-Performance Bus (AHB
nect implements a multilayer, nonblocking architecture that supports multiple simultaneous transactions
between masters and slaves, including the Cortex-A9 microprocessor unit (MPU) subsystem. The system
interconnect provides five independent L4 buses to access control and status registers (CSRs) of
peripherals, managers, and memory controllers.
Related Information
http://infocenter.arm.com
Additional information is available in the AMBA Network Interconnect (NIC-301) Technical Reference
Manual, revision r2p3, which you can download from the ARM info center website.

Features of the System Interconnect

The system interconnect supports high-throughput peripheral devices. The system interconnect has the
following characteristics:
• Main internal data width of 64 bits
• Programmable master priority with single-cycle arbitration
• Full pipelining to prevent master stalls
• Programmable control for FIFO buffer transaction release
• ARM TrustZone
• Multiple independent L4 buses
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