Altera cyclone V Technical Reference page 692

9-56
vid5wr_s
31 30
force Reserved
RO 0x0
15 14
Reserved
vid5rd_s Fields
Bit
31
force
27:16
mid
13:12
page
8:4
user
vid5wr_s
The Write AXI Master Mapping Status Register contains the configured USER, ADDR page, and ID
signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID.
Module Instance
acpidmap
Offset:
0x4C
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
page Reserved
RO 0x0
Name
Set to 1 to force the mapping between the 12-bit ID
and 3-bit virtual ID N. Set to 0 to allow the 3-bit ID N
to be dynamically allocated.
The 12-bit ID of the master to remap to 3-bit virtual
ID N, where N is the 3-bit ID to use.
ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory
region.
This value is propagated to SCU as ARUSERS.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
9 8 7 6
user
RO 0x0
Description
Base Address
0xFF707000
21 20 19 18
mid
RO 0x0
5 4 3
Register Address
0xFF70704C
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
17 16
2 1 0
Reserved
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
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