Sdram Controller Subsystem Block Diagram - Altera cyclone V Technical Reference

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SDRAM Controller Subsystem Block Diagram

SDRAM Controller Subsystem Block Diagram
The SDRAM controller subsystem connects to the MPU subsystem, the L3 interconnect, and the FPGA
fabric. The memory interface consists of the SDRAM controller, the physical layer (PHY), control and
status registers (CSRs), and their associated interfaces.
Figure 11-1: SDRAM Controller Subsystem High-Level Block Diagram
MPU
Subsystem
L3
Interconnect
FPGA
Fabric
SDRAM Controller
The SDRAM controller provides high performance data access and run-time programmability. The
controller reorders data to reduce row conflicts and bus turn-around time by grouping read and write
transactions together, allowing for efficient traffic patterns and reduced latency.
The SDRAM controller consists of a multiport front end (MPFE) and a single-port controller. The MPFE
provides multiple independent interfaces to the single-port controller. The single-port controller
communicates with and manages each external memory device.
The MPFE FPGA-to-HPS SDRAM interface port has an asynchronous FIFO buffer followed by a synchro‐
nous FIFO buffer. Both the asynchronous and synchronous FIFO buffers have a read and write data FIFO
depth of 8, and a command FIFO depth of 4. The MPU subsystem 64-bit AXI port and L3 interconnect
32-bit AXI port have asynchronous FIFO buffers with read and write data FIFO depth of 8, and command
FIFO depth of 4.
Altera Corporation
64-Bit AXI
32-Bit AXI
Multi-Port
Front End
FPGA-to-HPS
SDRAM Interface
32- to 256-Bit
AXI or
Avalon-MM
SDRAM Controller Subsystem
SDRAM Controller
Single-Port
Controller
Control & Status Registers
Register Slave Interface
L4 Peripheral Bus (l4_sp_clk)
Altera
PHY
Interface
DDR
PHY
SDRAM Controller Subsystem
cv_5v4
2016.10.28
HPS
External
I/O
Memory
Pins
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