Altera cyclone V Technical Reference page 443

cv_5v4
2016.10.28
Bit
1
trst
en
This register is used to enable one of the 5 scan-chains (0-3 and 7). Only one scan-chain must be enabled
at a time. A scan-chain is enabled by writing its corresponding enable field. Software must use the System
Manager to put the corresponding I/O scan-chain into the frozen state before attempting to send I/O
configuration data to the I/O scan-chain. Software must only write to this register when the Scan-Chain
Engine is inactive.Writing this field at any other time has unpredictable results. This means that before
writing to this field, software must read the STAT register and check that the ACTIVE and WFIFOCNT
fields are both zero. The name of this register in ARM documentation is PSEL.
Module Instance
scanmgr
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Scan Manager
Send Feedback
Name
Specifies the value of the nTRST signal driven to the
FPGA JTAG only. The FPGA JTAG scan-chain must
be enabled via the EN register to drive the value
specified in this field. The nTRST signal is driven with
the inverted value of this field.The nTRST signal is
active low so, when this bit is set to 1, FPGA JTAG is
reset. The name of this field in ARM documentation
is TRST_OUT.
Value
0x0
0x1
0xFFF02000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Description
Don't reset FPGA JTAG.
Reset FPGA JTAG. Must have the FPGA
JTAG scan-chain enabled in the EN register
to take effect.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
fpgaj Reserved
tag
RW
0x0
Access
Register Address
0xFFF02004
21 20 19 18
5 4 3 2
iosca iosca
nchai nchai
n3 n2
RW RW
0x0 0x0
6-11
en
Reset
RW 0x0
17 16
1 0
iosca ioscanch
nchai ain0
n1
RW 0x0
RW
0x0
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