Device Operation - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
For generic hub operations, the USB OTG controller uses SPLIT transfers to communicate with
slower-speed devices downstream of the hub. For these transfers, the transaction accumulation or
buffering is performed in the generic hub, and is scheduled accordingly. The USB OTG controller ensures
that enough transmit and receive buffers are allocated when the downstream transactions are completed
or when accumulated data is ready to be sent upstream.

Device Operation

Device Initialization
The following process sets up the USB OTG controller as a USB device:
1. After power up, the USB OTG controller must be set to the desired device speed by writing to the
Device Speed (
(
devgrp
as a device port.
2. When an external host detects the USB port, the host performs a port reset, which generates an
interrupt to the USB device software. The USB Reset (
register in the Global Registers (
buffer to receive a SETUP packet from the external host. Endpoint 0 is not enabled yet.
3. After completion of the port reset, the operation speed required by the external host is known. Software
reads the device speed status and sets up all the remaining required transaction fields to enable control
endpoint 0.
After completion of this process, the device is receiving SOF packets, and is ready for the USB host to set
up the device's control endpoint.
Device Transaction
When configured as a device, the USB OTG controller uses a single FIFO buffer to receive the data for all
the OUT endpoints. The receive FIFO buffer holds the status of the received data packet, including the
byte count, the data packet ID (PID), and the validity of the received data. The DMA controller reads the
data out of the FIFO buffer as the data are received. If a FIFO buffer overflow condition occurs, the
controller responds to the OUT packet with a NAK, and internally rewinds the pointers.
For IN endpoints, the controller uses dedicated transmit buffers for each endpoint. The application does
not need to predict the order in which the USB host will access the nonperiodic endpoints. If a FIFO
buffer underrun condition occurs during transmit, the controller inverts the cyclic redundancy code
(CRC) to mark the packet as corrupt on the USB link.
The application handles one data packet at a time per endpoint in transaction-level operations. The
software receives an interrupt on completion of every packet. Based on the handshake response received
on the USB link, the application determines whether to retry the transaction or proceed with the next
transaction, until all packets in the transfer are completed.
USB 2.0 OTG Controller
Send Feedback
) bits in the Device Configuration Register (
devspd
) group. After the device speed is set, the controller waits for a USB host to detect the USB port
globgrp
) bit in the Interrupt (
usbrst
) group is set. The device software then sets up the data FIFO
Device Operation
) in the Device Mode Registers
dcfg
port reset
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)