Altera cyclone V Technical Reference page 710

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Document Revision History
Date
December 2014
June 2014
February 2014
December 2013
November 2012
May 2012
January 2012
Altera Corporation
Version
2014.12.15
• Added bus transaction scenarios in the "Accelerator Coherency
Port" section
• Added the "AxUSER and AxCACHE Attributes" subsection to the
"Accelerator Coherency Port" section
• Added the "Shared Requests on ACP" subsection to the "Accelerator
Coherency Port" section
• Added the "Configuration for ACP Use" subsection to the "Acceler‐
ator Coherency Port" section
• Clarified how to use fixed mapping mode in the ACP ID Mapper
• Updated HPS Peripheral Master Input IDs table
• Added a note to the "Control of the AXI User Sideband Signals"
subsection in the "ACP ID Mapper" section.
• Added parity error handling information to the "L1 Caches" section
and the "Cache Controller Configuration" topic of the "L2 Cache"
section.
2014.06.30
• Added Reset Section to Cortex-A9 Processor
• Updated HPS Peripheral Master Input IDs table
• Added ACP ID Mapper Address Map and Register Definitions
• Added information in ECC Support section regarding ECC errors
• Minor clarifications regarding MPU description and module
revision numbers
2014.02.28 Maintenance release
2013.12.30
Correct SDRAM region address in ARM Cortex-A9 MPCoreAddress
Map
1.2 Minor updates.
1.1 • Add description of the ACP ID mapper
• Consolidate redundant information
1.0 Initial release.
Changes
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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