Fpga Status; Error Message Extraction; Boot Handshake - Altera cyclone V Technical Reference

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FPGA Status

FPGA Status
Configuration signals from the FPGA CB such as
the FPGA Manager. Software configures the monitor block through the register slave interface, and can
either poll FPGA signals or be interrupted. Monitored signals can be read through the
register as well as the
interrupt to the MPU global interrupt controller. Each interrupt source can be enabled and the polarity of
the signals generating the interrupt can also be selected through the
registers in the FPGA Manager.

Error Message Extraction

Cyclic redundancy check (CRC) errors from the FPGA fabric are monitored by the FPGA Manager. Upon
assertion of a CRC error signal from the FPGA, the FPGA Manager extracts information about the error
including:
• Error syndrome
• Error location
• Error type
A CRC error interrupt from the FPGA manager can be enabled through software. Software can then
extract the CRC error information from the error message register (EMR) data interface. The number of
valid error information bits in the EMR data registers depends on the specific FPGA device.

Boot Handshake

There are two input signals from the FPGA to control HPS boot from the FPGA. Both are synchronized
within the FPGA Manager. Boot software reads these signals before accessing a boot image in the FPGA.
The following table describes the functionality of these signals.
f2h_boot_from_fpga_on_failure
f2h_boot_from_fpga_ready
Altera Corporation
intr_masked_status
Signal
,
INIT_DONE CRC_ERROR
register. Each of the monitored signals can generate an
Indicates whether a fallback preloader image is available in the
FPGA on-chip RAM at memory location 0x0. The fallback
preloader image is used only if the HPS boot ROM does not
find a valid preloader image in the selected flash memory
device. It is an active high signal which the bootrom polls when
all the preloaders fail to load. This signal is driven low when the
FPGA is not configured and it is up to you to drive it high in
your user design.
Indicates a preloader image is available in an FPGA on-chip
RAM at memory location 0x0 and it is ready to be accessed. It is
an active high signal which the bootrom polls to determine
when the FPGA is configured and the memory located at offset
0x0 from the F2H bridge is ready to be written to. When the
FPGA is not configured the hardware will drive this signal low
and it is up to you to drive it high when the memory in the
FPGA is ready to accept memory mapped transactions.
and are monitored by
PR_DONE
imgcfg_stat
and
intr_mask intr_polarity
Description
cv_5v4
2016.10.28
FPGA Manager
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